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INTEGRATED CIRCUITS
DATA SHEET
SAA7392 Channel encoder/decoder CDR60
Preliminary specification File under Integrated Circuits, IC01 2000 Mar 21
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
CONTENTS 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 8 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description FUNCTIONAL DESCRIPTION Microprocessor interfaces Register map System clocks HF analog front-end Bit recovery Decoder function Subcode interface Digital output Serial output interface Motor control The serial in function The subcode insert function The data encoder block Encode control block The EFM modulator The EFM clock generator The Wobble processor LIMITING VALUES 10.7 11 12 12.1 12.2 12.3 12.4 12.5 13 14 15 9 9.1 10 10.1 10.2 10.3 10.4 10.5 10.6
SAA7392
OPERATING CHARACTERISTICS ADC and AGC parameters APPLICATION INFORMATION Write start control of encoder in CD-ROM mode Write start control of encoder in Audio mode Start-up of encode in flow-control operation Start-up of encoder in synchronous stream mode Operating CDR60 in CAV mode, flow control on input stream Operating in CLV Mode, Flow Control on Input Stream Operating in CLV Mode, Synchronous Stream Operation PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
2000 Mar 21
2
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
1 FEATURES
SAA7392
* Very high speed Compact Disc (CD) compatible decoding and encoding device * On-chip Analog-to-Digital Converter (ADC) and Automatic Gain Control (AGC) for HF data capture * Eight-to-Fourteen Modulation (EFM) * Advanced motor control loop to allow CAV, CLV and pseudo-CLV playback * Integrated FIFO for de-coupling of mechanism speed and application speed * Versatile output interface allowing different I2S-bus and Electronic Industries Association of Japan (EIAJ) formats * Device is fully compatible with ELM, PLUM and Sanyo CD-ROM block decoders * Quad-pass CIRC correction for CD mode (C1-C2-C1-C2) * Subcode/header processing for CD format * Frequency multiplier allows use of a 8 MHz crystal. 2 GENERAL DESCRIPTION The bit detector recovers the individual bits from the incoming signal, correcting asymmetry, performing noise filtering and equalisation, and recovering the channel bit clock using a digital PLL. The demodulator converts the EFM bits to byte-wide data symbols, before passing them onto the decoder for subcode extraction, de-interleaving and error correction. The decoded data is then made available via the multi-function serial output interface. The encode datapath takes data symbols from the block encoder/decoder via the serial data and subcode input functions, encoding them via the encoder block. The encoded data stream is passed to the EFM modulator, which generates the required EFM signal, output as a digital bit stream. The encode process is controlled via the Wobble processor, encode control and EFM clock generator functions. As well as these two data processing sections, three further blocks support overall device operation. The system clock generator provides all digital clocks required by the CDR60. The motor servo allows the CDR60 to control the spindle motor and is controlled by the microprocessor interface. This interface can be accessed either via a parallel (80C51) or a serial (I2C-bus) interface.
CDR60 is a channel encoder/decoder for CD/CD-R/CD-RW/CD Audio Recorder systems. It incorporates all logic and RAM required for the complete encoding and decoding processes. There are two main datapaths through the CDR60 device. The decode datapath captures the incoming EFM data stream via the HF ADC and AGC functions. 3 QUICK REFERENCE DATA SYMBOL VDDD VDDA VDDE IDD fxtal Tamb Tstg 4 PARAMETER supply voltage (core and pad ring) supply voltage (analog) supply voltage (output drivers) supply current crystal frequency operating ambient temperature storage temperature
MIN. 3.0 3.0 3.0 - 8 0 -55 3.3 3.3 3.3 200
TYP. 3.6 3.6 3.6 - 33 70
MAX. V V V mA
UNIT
8.4672 - -
MHz C C
+125
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME LQFP80 DESCRIPTION plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm 3 VERSION SOT315-1
SAA7392HL 2000 Mar 21
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2000 Mar 21
IREF VREF 8 7 IREF GENERATOR OTD T1 T2 MOTO2/T3 MOTO1 VSSA1 VDDA1 VDDA2 VSSA2 VDDD VSSD VDDE 23 70 69 73 74 4 5 15 16 30, 49, 53, 76 19, 31, 43, 48, 52, 62, 71, 75 20, 44, 63, 72
5
Philips Semiconductors
Channel encoder/decoder CDR60
BLOCK DIAGRAM
WREFMID WREFLO 1
WIN
W441 XEFM 25 78
PANIC EFMDATA 79 EFM MODULATOR LASERON 77 27 65 SUBCODE INSERT 67 66 SUB SFSY RCK
WREFHI ATIPSYC 3 2 6 26
WOBBLE PROCESSOR
EFM CLOCK GENERATOR
ENCODE CONTROL
64 SERIAL IN MOTOR/TACHO INTERFACE 60
DATAI WCLK
61 ERROR CORRECTOR AND MEMORY PROCESSOR 57 55 SERIAL OUT 56 59 54 BIT DETECTOR DE-MODULATOR 58 51
BCLK SYNC V4 EBUOUT DATAO STOPCK FLAG PCAin
4
SAA7392
HF DATA CAPTURE
SYSTEM CLOCK GENERATOR
RESET
TEST CONTROL 35 to 42
SUB-CPU INTERFACE
11 HREFLO
14
10
13
12
80
29 CL1
24
22
21
28 PORE
18
17
68
47
46
45
50
32
33
34
MGR791
Preliminary specification
HREFHI AGCREF HIN
XTLO XTLI
HREFMID
MEAS1 MUXSWI
DA7 TEST2 TEST1 CSi SDA RDi SCL INT WRi CFLG to ALE DA0
SAA7392
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
6 6.1 PINNING INFORMATION Pinning
SAA7392
77 LASERON
79 EFMDATA
handbook, full pagewidth
73 MOTO2/T3
74 MOTO1
80 MEAS1
64 DATAI
76 VDDD
72 VDDE
63 VDDE
78 XEFM
75 VSSD
71 VSSD
62 VSSD
68 CFLG
67 SFSY
WREFLO WREFHI WREFMID VSSA1 VDDA1 WIN VREF IREF n.c.
1 2 3 4 5 6 7 8 9
61 BCLK 60 WCLK 59 DATAO 58 FLAG 57 SYNC 56 EBUOUT 55 V4 54 STOPCK 53 VDDD 52 VSSD 51 PCAin 50 CSi 49 VDDD 48 VSSD 47 ALE 46 RDi 45 WRi 44 VDDE 43 VSSD 42 DA0 41 DA1 DA2 40
66 RCK DA7 35
HREFHI 10
SAA7392
HREFLO 11 AGCREF 12 HIN 13 HREFMID 14 VDDA2 15 VSSA2 16 TEST1 17 TEST2 18 VSSD 19 VDDE 20 XTLI 21 XTLO 22 OTD 23 MUXSWI 24 W441 25 ATIPSYC 26 PANIC 27 PORE 28 CL1 29 VDDD 30 VSSD 31 SCL 32 SDA 33 INT 34 DA6 36 DA5 37 DA4 38 DA3 39
65 SUB
70 T1
69 T2
MGR792
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
6.2 Pin description LQFP80 package; note 1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19, 43, 62, 71 20 21 22 23 24 25 26 27 28 29 30, 49, 53, 76 31, 48, 52, 75 32 33 34 35 36 37 38 TYPE O O O supply supply I O O - O O I I O supply supply I I supply supply I O I I O O I I O supply supply I I/O O I/O I/O I/O I/O DESCRIPTION wobble ADC analog reference voltage wobble ADC analog reference voltage wobble ADC analog reference voltage analog ground 3 V analog supply voltage 1; note 2 wobble analog input analog voltage reference analog current reference not connected HF ADC analog reference voltage HF ADC analog reference voltage AGC analog reference voltage HF analog data input HF ADC analog reference voltage 3 V analog supply voltage 2; note 2 analog ground test input 1 test input 2 output driver ground output driver 3 V supply voltage crystal oscillator input crystal oscillator output off track detect input clock multiplier enable wobble 44.1 kHz clock output ATIPSync output laser low power (LLP) power-on reset divided clock output core and pad ring 3 V supply voltage; note 2 core and pad ring ground sub-CPU clock bidirectional sub-CPU data sub-CPU interrupt bidirectional sub-CPU parallel data bus bidirectional sub-CPU parallel data bus bidirectional sub-CPU parallel data bus bidirectional sub-CPU parallel data bus
SAA7392
Table 1
SYMBOL WREFLO WREFHI WREFMID VSSA1 VDDA1 WIN VREF IREF n.c. HREFHI HREFLO AGCREF HIN HREFMID VDDA2 VSSA2 TEST1 TEST2 VSSD VDDE XTLI XTLO OTD MUXSWI W441 ATIPSYC PANIC PORE CL1 VDDD VSSD SCL SDA INT DA7 DA6 DA5 DA4
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
SYMBOL DA3 DA2 DA1 DA0 VDDE WRi RDi ALE CSi PCAin STOPCK V4 EBUOUT SYNC FLAG DATAO WCLK BCLK VDDE DATAI SUB RCK SFSY CFLG T2 T1 VDDE MOTO2/T3 MOTO1 LASERON XEFM EFMDATA MEAS1 Notes
PIN 39 40 41 42 44 45 46 47 50 51 54 55 56 57 58 59 60 61 63 64 65 66 67 68 69 70 72 73 74 77 78 79 80
TYPE I/O I/O I/O I/O supply I I I I I O O O O O O I/O I/O supply I I O I O I I supply I/O O O O O O
DESCRIPTION bidirectional sub-CPU parallel data bus bidirectional sub-CPU parallel data bus bidirectional sub-CPU parallel data bus bidirectional sub-CPU parallel data bus output driver 3 V supply voltage sub-CPU write enable; active LOW sub-CPU read enable; active LOW sub-CPU address latch enable sub-CPU chip select PCA input stop clock output serial subcode output digital output I2S sector sync output I2S correction flag I2S data output bidirectional I2S word clock bidirectional I2S bit clock output driver 3 V supply voltage I2S data input EIAJ subcode data EIAJ subcode clock EIAJ subcode sync correction statistics; open-drain tacho control input 2 tacho control input 1 output driver 3 V supply voltage motor output 2/tacho input 3 motor control output 1 laser write control EFM clock output EFM data output front end telemetry; open-drain
1. No signal may be applied to this device when it is not powered. 2. The analog and digital supply pins (VDDA and VDDD) must be connected to the same external supply.
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7 7.1 FUNCTIONAL DESCRIPTION Microprocessor interfaces
SAA7392
The sequence for a write data command is as follows: 1. Send START condition 2. Send address 3EH (write) 3. Write register address byte 4. Write data byte 5. Send STOP condition. The sequence for a read data command is as follows: 1. Send START condition 2. Send address 3EH (write) 3. Write status register address byte 4. Send STOP condition 5. Send address 3FH (read) 6. Read data byte 7. Send STOP condition. 7.1.2 PARALLEL INTERFACE
The SAA7392 is programmed via two independent microprocessor interfaces: * Serial I2C-bus I2C-bus I2C-bus data clock - SDA = - SCL = - -
I2C-bus I2C-bus
write address = 3EH read address = 3FH.
* Parallel 80C51 compatible - DA(7:0) = address/data bus - ALE = address latch enable; latches the address information on the bus - WRi = active LOW write signal; write to SAA7392 - RDi = active LOW read signal; read from SAA7392 - CSi = chip select signal; gates the RDi and WRi signals. 7.1.1 SERIAL I2C-BUS INTERFACE
Data is transferred over the interface in single bytes, via write data or read data commands.
The parallel interface has a multiplexed address/data bus. Information can be written to or read from the SAA7392 using the protocols shown in Figs 3 and 4; specific timings are shown in Table 2. Note that only the lower six address bits are decoded; so writing to address 40H would have the same effect as writing to address 00H.
handbook, full pagewidth
td1 ALE t WRiL WRi td2 th1 CSi
DA0 to DA7
address (0:7) IN
data (0:7) IN
MGR793
tsu1 th2
tsu2
Fig.3 Microprocessor write protocol.
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
handbook, full pagewidth
td1 ALE RDiL RDi td2 th1 CSi
DA0 to DA7
address (0:7) IN
data (0:7) OUT
MGR794
tsu1 th2
Fig.4 Microprocessor read protocol.
Table 2
Parallel interface timing DESCRIPTION Delay ALE falling to RDi/WRi falling. Delay CSi rising to RDi/WRi falling. CSi hold time after RDi/WRi falling. Address setup time before ALE falling. Address hold time after ALE falling. Data setup time before WRi falling. Data hold time after WRi falling. WRi LOW time. ALE LOW hold time after WRi LOW. Delay data valid after RDi LOW. Delay RDi HIGH to data out high-impedance. RDi LOW time. 17 17 2Tclk + 17 17 17 0 2Tclk + 17 1Tclk + 17 3Tclk + 17 - - 3Tclk + 128 MIN.(1) - - - - - - - - - 3Tclk + 17 17 - MAX.(1) ns ns ns ns ns ns ns ns ns ns ns ns UNIT
SYMBOL td1 td2 th1 tsu1 th2 tsu2 th3 tWRiL th4 td3 td4 tRDiL Note 1. Tclk is the system clock period.
2000 Mar 21
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Channel encoder/decoder CDR60
Table 3
Register map REGISTER NAME PLL Lock Select Register (PLLLock) PLL Bandwidth Select Register (PLLSet) PLL Frequency Preset Register (PLLFreq) PLL Equalizer Preset Register (PLLEqu) PLL Lock Aid2 Preset Register (PLLFMeas) I2S I2S Output Register 1 (Output1) Output Register 2 (Output2) TYPE Write Read Write Read Write Read Write Read Write Write Write Write FUNCTION PLL lock select 8-bit PLL frequency PLL bandwidth select 8-bit asymmetry signal PLL frequency preset 8-bit jitter signal PLL equalizer preset Observe internal lock flags PLL lock aid 2 preset I2S I2S output 1 output 2 BLOCK RESPONSIBLE bit detector bit detector bit detector bit detector bit detector bit detector bit detector bit detector bit detector serial out serial out serial out sub-CPU sub-CPU sub-CPU sub-CPU sub-CPU motor/tacho bit detector motor/tacho bit detector motor/tacho motor/tacho motor/tacho motor/tacho
ADDRESS (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0B 0C
I2S Output Register 3 (Output3) Semaphore Register 1 (Sema1) Semaphore Register 2 (Sema2) Semaphore Register 3 (Sema3) Interrupt Enable Register (IntEn) Status Register (Status) Motor Control Register 1 (Motor1)
I2S output 3
Write/Read Inter-microprocessor communication Write/Read Inter-microprocessor communication Write/Read Inter-microprocessor communication Write Read Write Read Enable interrupts Interrupt status Frequency set-point 8-bit slicer compensation value Motor coefficient preset Opening of eye pattern Motor integrator preset Motor control
0D 0E 0F 10 11
Motor Mode Select Register 2 (Motor2) Motor Control Register 3 (Motor3) Motor Control Register 4 (Motor4) Motor Control Register 5 (Motor5) Motor Control Register 6 (Motor6)
Write Read Write Read Write
Preliminary specification
SAA7392
Read back of motor frequency motor/tacho
Read/Write Motor integrator value Read/Write Motor integrator value
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Channel encoder/decoder CDR60
Read/Write Interrupt status Write Write Read Write Write
Read/Write Subcode control Read/Write Subcode data
SAA7392
Read/Write 8 MSBs of PLL frequency Read/Write 8 LSBs of PLL frequency Read ATIP data
Wobble processor Wobble processor Wobble processor
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Channel encoder/decoder CDR60
Read/Write Laser and data flow control
Preliminary specification
SAA7392
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.2.1 INTERRUPT PIN
SAA7392
The interrupt pin (INT) is the AND-OR-INVERT of the Status and Interrupt Enable Registers, i.e. INT will become active when corresponding bits are set at the same time in the Status and Interrupt Enable Registers. 7.2.2 THE SEMAPHORE REGISTERS (SEMA1, SEMA2 AND SEMA3)
The Semaphore Registers are intended for inter-microprocessor communications. For example, microcontroller 1 can write data to microcontroller 2 via Sema1 and microcontroller 2 can write data to microcontroller 1 via Sema2. The Status Register of the SAA7392 offers a mechanism so that both microcontrollers can see when new data has been written and when it has been read by looking at the contents of the Semaphore Registers. Version M3 of the CDR60 can be identified by writing and reading register Sema3. In version M3, bit 1 of Sema3 is always read as logic 0, whereas in other CDR60 versions this bit reads the same value as what was written to it before.
7.2.2.1
Table 4 7
Semaphore Register 1 (Sema1)
Semaphore Register 1 (address 08H) - READ/WRITE 6 Sema1.6 5 Sema1.5 4 Sema1.4 3 Sema1.3 2 Sema1.2 1 Sema1.1 0 Sema1.0
Sema1.7
7.2.2.2
Table 5 7
Semaphore Register 2 (Sema2)
Semaphore Register 2 (address 09H) - READ/WRITE 6 Sema2.6 5 Sema2.5 4 Sema2.4 3 Sema2.3 2 Sema2.2 1 Sema2.1 0 Sema2.0
Sema2.7
7.2.2.3
Table 6 7
Semaphore Register 3 (Sema3)
Semaphore Register 3 (address 0AH) - READ/WRITE 6 Sema3.6 5 Sema3.5 4 Sema3.4 3 Sema3.3 2 Sema3.2 1 Sema3.1 0 Sema3.0
Sema3.7 7.2.3 Table 7 7 Sema1 Table 8 BIT 7 6 5 4 3 2 1 0
STATUS REGISTER (STATUS) Status Register (address 0BH) - READ 6 Sema2 5 Sema3 4 LockIn 3 HeaderVal 2 MotorOverflow 1 FIFOOv 0 -
Description of Status bits SYMBOL Sema1 Sema2 Sema3 LockIn HeaderVal FIFOOv - DESCRIPTION If Sema1 = 1, change in register Sema1 has been detected. Reset if register Sema1 read. If Sema2 = 1, change in register Sema2 has been detected. Reset if register Sema2 read. If Sema3 = 1, change in register Sema3 has been detected. Reset if register Sema3 read. If LockIn = 1, then channel data PLL in lock (not latched). HeaderVal is set when new header/subcode is available; reset on reading SubReadEnd. If FIFOOv = 1, then the FIFO has overflowed. This bit is reserved.
MotorOverflow If MotorOverflow = 1, then a motor overflow is occurring (not latched).
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.2.4 Table 9 7 Sema1En INTERRUPT ENABLE REGISTER (INTEN) Interrupt Enable Register (address 0BH) - WRITE 6 Sema2En 5 Sema3En 4 LockInEn 3 2 1
SAA7392
0 -
HeaderValen MotorOverflowEn
FIFOOvEn
Table 10 Description of IntEn bits BIT 7 6 5 4 3 2 1 0 7.2.5 SYMBOL Sema1En Sema2En Sema3En LockInEn HeaderValEn FIFOOvEn - DESCRIPTION If Sema1En = 1, then Semaphore Register 1 interrupt is enabled. If Sema2En = 1, then Semaphore Register 2 interrupt is enabled. If Sema3En = 1, then Semaphore Register 3 interrupt is enabled. If LockinEn = 1, then channel data PLL in lock interrupt is enabled. If HeaderValEn = 1, then new header/subcode available interrupt is enabled. If FIFOOvEn = 1, then FIFO overflow interrupt is enabled. This bit is reserved.
MotorOverflowEn If MotorOverflowEn = 1, then motor overflow interrupt is enabled.
STATUS REGISTER 2 (STATUS2)
Table 11 Status Register 2 (address 20H) - READ/WRITE 7 BankSwitch 6 SyncError 5 DataNotValid 4 QSync 3 ATIPSync 2 LaserOn 1 LaserOff 0 XErrorLarge
Table 12 Description of Status2 bits BIT 7 6 5 4 3 2 1 0 SYMBOL BankSwitch SyncError DataNotValid QSync ATIPSync LaserOn LaserOff XErrorLarge DESCRIPTION When set a `Bank switch' in the subcode insert block has occurred; reset when a logic 1 is written to this bit. When set synchronisation with PLUM on subcode transfer has failed; reset when a logic 1 is written to this bit. When set an under-run on subcode transfer with PLUM has occurred; reset when a logic 1 is written to this bit. When set a Q-channel subcode sync has been written to disc; reset when a logic 1 is written to this bit. When set sync has been found in the ATIP channel; reset when a logic 1 is written to this bit. When set a rising edge of the internal LaserOn signal has occurred; reset when a logic 1 is written to this bit. When set a falling edge of the internal LaserOn signal has occurred; reset when a logic 1 is written to this bit. When set the offset between QSync and ATIPSync is more than 2 EFM frames different from the programmed value.
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.2.6 INTERRUPT ENABLE REGISTER 2 (INTEN2)
SAA7392
Table 13 Interrupt Enable Register 2 (address 21H) - WRITE 7 BankSwitch En 6 SyncErrorEn 5 DataNotValid En 4 QSyncEn 3 ATIPSyncEn 2 LaserOnEn 1 LaserOffEn 0 XErrorLarge En
Table 14 Description of IntEn2 bits BIT 7 6 5 4 3 2 1 0 SYMBOL BankSwitch En DataNotVali dEn QSyncEn LaserOnEn LaserOffEn DESCRIPTION If BankSwitchEn = 1, then BankSwitch interrupt is enabled.
SyncErrorEn If SyncErrorEn = 1, then SyncError interrupt is enabled. If DataNotValidEn = 1, then DataNotValid interrupt is enabled. If QSyncEn = 1, then QSync interrupt is enabled. If LaserOnEn = 1, then LaserOn interrupt is enabled. If LaserOffEn = 1, then LaserOff interrupt is enabled.
ATIPSyncEn If ATIPSyncEn = 1, then ATIPSync interrupt is enabled.
XErrorLarge If XerrorLarge = 1, then XErrorLarge interrupt is enabled. En SOFT RESET REGISTER (SOFTRESET)
7.2.7
Table 15 Soft Reset Register (address 1BH) - WRITE 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 SReset1
Table 16 Description of SoftReset bits BIT 7 to 1 0 SYMBOL - SReset1 These 7 bits are reserved. When set, synchronisation with PLUM on subcode transfer has failed; reset when a logic 1 is written to this bit (Status2). This bit is an active HIGH reset to the following blocks: Encoder/decoder, EFM modulator, Encode control block, Serial input/output block and Encode subcode insert block. The clock control, EFM PLL, tacho, motor interface and wobble interface remain running. Soft reset will reset the following registers: EFMPresetCount, EFMModulateConfig, EFMModulateConfig2, EncodeXOffset, EncodeWriteControl, EncodeStartOffset, EncodeStopOffset, SubPresetCount, SubConfig1, Subconfig2, SubStartData, SubData, InputConfig, DecoMode, Output1, Output2 and Output3. A soft reset is mandatory in the following cases: 1. After programming the BCLK clock 2. When switching from encode to decode 3. When switching from decode to encode. DESCRIPTION
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.3 System clocks
SAA7392
The principle clocks used in the SAA7392 are derived from the crystal oscillator input pin XTLI (alternatively, an external clock can be connected to this pin). These clocks are the system clock (also used as the ADC clock) and the I2S output bit clock (BCLK). The system clock (fclk) defines the maximum operational channel rate for the device. The maximum EFM channel clock is twice the system clock, for CD it is equivalent to system clock/(4.3 x 106) which is approximately 11.5 x CDROM for a 25 MHz system clock. The other clock in the system is the channel data clock, this is recovered by the front-end bit recovery PLL.
handbook, full pagewidth
MUXSWI
x
XTLI crystal oscillator XTLO CL1 CL1 DIVIDER CLOCK (1) MULTIPLIER
M x XTLI
SYSTEM CLOCK DIVIDER
system clock
XTLI
BIT CLOCK DIVIDER
BCLK
system clock
MGR795
(1) M = 1 if MUXSWI is LOW; M = 8 if MUXSWI is HIGH.
Fig.5 System clock generator.
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.3.1 CLOCK PRESET REGISTER (CLOCKPRE)
SAA7392
Table 17 Clock Preset Register (address 12H) - WRITE 7 CL1Div 6 GateBClk 5 Div.1 4 Div.0 3 Mux2 2 Div2.2 1 Div2.1 0 Div2.0
Table 18 Description of ClockPre bits BIT 7 6 SYMBOL CL1Div GateBClk DESCRIPTION If CL1Div = 0, then CL1 output frequency is 13fclk. If CL1Div = 1, then CL1 output frequency is 12fclk. If GateBClk = 0, then I2S output bit clock gating is disabled. If GateBClk = 1, then I2S output bit clock gating enabled, BCLK is output, clock is automatically stopped if FIFO underflows (this is known as Flow control mode). These 2 bits select the system clock frequency (fclk); see Table 19. This frequency should be programmed for the expected disc channel rate (e.g. 4.33 MHz for 1 x CD) within the following constraints: Channel rate --------------------------------- < f clk < 4 x Channel rate 2 In this clock range, reliable bit detection is possible. All data found will be written to the FIFO. It is the responsibility of the user to select system clock values so that the FIFO performance is controlled. 3 2 to 0 Mux2 Div2<2:0> If Mux2 = 0, then N (bit clock divider pre-scaler) = 1. If Mux2 = 1, then N = M. These 3 bits select the BCLK frequency (fBCLK); see Table 20. It is the responsibility of the user to select BCLK values so that the FIFO performance is controlled.
5 4
Div.1 Div.0
Table 19 Selection of system clock frequency Div.1 0 0 1 1 Div.0 0 1 0 1 M x fXTLI 0.5 x M x fXTLI 0.25 x M x fXTLI 0.125 x M x fXTLI SYSTEM CLOCK FREQUENCY (fclk)
Table 20 Selection of BCLK frequency Div2.1 0 0 0 0 1 1 1 1 Div2.1 0 0 1 1 0 0 1 1 Div2.0 0 1 0 1 0 1 0 1 N x fXTLI N x fXTLI
1/ 1/ 1/ 1/ 1/ 1/ 2(N 3(N
BCLK FREQUENCY (fBCLK)
x fXTLI) x fXTLI) x fXTLI) x fXTLI)
4(N x fXTLI) 6(N 8(N
12(N x fXTLI)
2000 Mar 21
17
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.4 HF analog front-end
SAA7392
3. Instructions to increment/decrement gain are ignored when the AGC gain limits of -4/+12 dB are reached. 7.4.2 AUTOMATIC GAIN CONTROL (AGC)
The HF ADC in the SAA7392 encodes the EFM high frequency signal from the disc light pen assembly. These signals are pre-processed, externally to the SAA7392, by either AEGER-2 or a DALAS equivalent. The dynamic range of the ADC is optimized by the inclusion of an AC coupled AGC function under digital control. In order to make use of the whole digital front-end resolution, the output of the gain control amplifier should constantly deliver 1.4 V(p-p) output signal. The gain range of the ADC is approximately 14 dB, with 32 steps. The gain control for the variable gain amplifier is controlled by an on-chip digital gain control block (AGC). This block allows for both automatic and microprocessor gain control. The gain control block will detect ADC extreme conditions (00H or FFH outputs); on these values the gain control block will decrement the gain. If no extreme codes occur the gain is incremented. 7.4.1 FIXED GAIN
The gain of the AGC cell is adjusted until the analog signal at the ADC input extends over the complete range of the ADC. Detection of this condition is in the digital domain where the maximum and minimum ADC codes are measured. The dynamics of the AGC system are as follows. 1. If the ADC output codes are not full scale (i.e. 000 0000 and 111 11111) the AGC gain is incremented in 1.1 dB steps with a time constant of 1000/n s, where n is the over-speed factor i.e. n = 1 for basic audio CD. 2. When full scale is detected at the output of the ADC the AGC gain is fixed provided that full scale is maintained and clipping does not occur for greater than 20% of the time. 3. If clipping occurs for more than 20% of the time, then the AGC gain is reduced in 1.1 dB steps with a time constant of 60/n s. The ADC and AGC electrical characteristics are specified in Chapter 9.
Control of the gain is as follows: 1. Writing XX1X XXXX to the Anaset1 register (address 15H) increases the AGC gain by 1.1 dB 2. Writing XX0X XXXX to the AnaSet1 register (address 15H) decreases the AGC gain by 1.1 dB 7.4.3 ANALOG SETTINGS REGISTER 1 (ANASET1)
Table 21 Analog Settings Register 1 (address 15H) - WRITE 7 GainControl 6 MaxGain 5 StepUp 4 StepDown 3 PowerDown 2 - 1 - 0 -
Table 22 Description of AnaSet1 bits BIT 7 6 5 4 3 2 to 0 SYMBOL DESCRIPTION
GainControl If GainControl = 0, then gain control is in Hold mode. If GainControl = 1, then automatic gain control is on. MaxGain StepUp StepDown PowerDown - If MaxGain = 0, then there is no gain limit. If MaxGain = 1, then the maximum gain is 7.66 dB. If StepUp = 1, then step up gain by one LSB. If StepDown = 1, then step down gain by one LSB. If PowerDown = 0, then analog blocks are powered up. If PowerDown = 1, then analog blocks are powered down. These 3 bits are reserved and must be set to a logic 0s.
2000 Mar 21
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.5 Bit recovery
SAA7392
The slice level determination circuit compensates the incoming signal asymmetry component. The bandwidth of this circuit is programmable via register PLLSet. A programmable (one tap presetable, asymmetrical) equaliser is used in the bit detection circuit. The first and last tap settings are different. Possible tap values are settable via register PLLEqu. The advanced detector has two extra detection circuits (adaptive slicer and run length 2 push-back) which are controlled via the VitSet register, that allow improved margin in the bit detector. The adaptive slicer does a second stage slice operation; the bandwidth is higher than the first slicer. It can be turned on/off via the VitSet register. If the advanced detector is switched on all run length 2 symbols are pushed back to run length 3. The circuit will determine the transition that was most likely to be in error, and shift the transition on that edge.
The bit recovery block (shown in Fig.6) contains the slice level circuitry, a noise filter to limit the HF-EFM signal noise contribution, an adaptive slicer circuit and a digital PLL. These blocks can be controlled via the microprocessor. The channel rate should always obey the following constraints: * It should be less than 2 x the system clock * It should be greater than 0.25 x the system clock. In this clock range reliable bit clock detection is possible. All data found will be written to the FIFO. It is the responsibility of the user to select BCLK and system clock values so that the FIFO operation is controlled. The digital noise filter runs on the PLL bit clock and limits the bandwidth of the incoming signal to 0.25 of the PLL bit clock frequency. The characteristics of the filter are: * Passband: 0 to 0.22 fb * Stopband: 0.28 fb to (fclk - 0.28 fb) * Rejection: -28 dB.
GAIN CONTROLLED handbook, full pagewidth AMPLIFIER HIN ADC
+
-
GAIN CONTROL BLOCK
+
NOISE FILTER
DIGITAL EQUALIZER
VITERBI DETECTOR
SLICE LEVEL DETERMINE clocked on PLL clock
ZERO TRANS DETECTOR
DIGITAL PLL
RMS JITTER MEASUREMENT
MULTIPLEXER jitter value PLL frequency slice level
MGR796
MEAS1
Fig.6 Block diagram of bit recovery block.
2000 Mar 21
19
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.5.1 DIGITAL PLL
SAA7392
* PLL frequency signal: the most significant 8 bits are available via register PLLLock * Asymmetry signal: the 8-bit signal in 2's complement form is available via register PLLSet * Jitter signal: the most significant 8 bits are available via register PLLFreq. This gives an impression of the detection jitter after all processing is done. jitter<9:0> = average ((jitter individual transition)2 x 8192) To obtain the jitter in the bit clocks the jitter<9:0> value must be divided by 8192 and square routed. Note that the jitter<9:0> overestimates the jitter (by approximately rms jitter increase of 0.03 bit clock), because the quantization of the zero transitions is in 4 intervals. Note the jitter is measured before the bit detection and contains contributions due to various imperfections in the complete signal path; i.e. disc, preamplifier, ADC, limited bitwidths, PLL performance, internal filter noise, asymmetry compensation, equalizer. * Internal lock flags: The internally generated inner-lock signal (f_lock_in), lock signal (lock_in) and flag that indicates when a run length 14 is detected (long_symbol) are available via register PLLEqu.
The digital PLL will recover the channel bit clock. As the capture range of the PLL itself is limited, lock detectors and 2 capture aids are present. In total three different PLL operation modes exist: In-lock, Inner-lock aid and Outer-lock aid. The PLL behaviour during in-lock (the normal on-track situation) can be best explained in the frequency domain. The PLL operation is completely linear during in-lock situations. The open-loop response of the PLL is given in Fig.7. The three frequencies, f0 (integrator cross-over frequency), f1 (PLL bandwidth) and f2 (low-pass bandwidth) are programmable via register PLLSet. To extend the PLL capture range two lock aids are used: * Inner lock aid: has a capture range of 10% and will bring the PLL frequency to the lock point * Outer lock range: has no limitation on capture range, and will bring the PLL within the range of the inner lock range. Two outer lock aids can be used: * Run length 3 deviation detector: this circuit is known to be sensitive to systematic over/under equalization; this over/under equalization can be counter-acted by writing a non-zero phase offset value to register PLLLock. * Frequency measurement detector: this circuit regulates the PLL frequency so that the average number of EFM transitions is a fixed fraction of the PLL bit clock; the transition frequency is settable via register PLLFMeas. Programmability/observability is built into the PLL. Its operation can be influenced in two ways: * It is possible to select the state the PLL is in (in-lock, near-lock, outer-lock) via register PLLLock * It is possible to preset the PLL frequency to a certain value via registers PLLEqu and PLLFreq. The operation of the bit detector can be monitored by the microprocessor and via the MEAS1 pin. Four signals are available for measurement:
handbook, halfpage
amplitude (dB)
f2 f0 f1 frequency (Hz)
MGR797
Fig.7 PLL bode diagram.
2000 Mar 21
20
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.5.2 MEAS1 PIN
SAA7392
The MEAS1 pin carries the 3 measurement signals: jitter (sampled twice), PLL frequency, and asymmetry. Each frame consists of 64 bits (each 4 system clock periods long), beginning with a start bit, then data bits then pause bits (see Fig.8). The start bit is always preceded by 17 pause bits; and the intermediate start bits at locations 12, 24 and 36 guarantee that no other `1' bit is preceded by 17 `0' bits, making the start detection easy. The structure of the frame is described in Table 23 and shown in Fig.8. Table 23 Frame structure BIT 0 1 to 10 11 12 13 to 22 23 24 25 to 32 33 34 37 to 46 47 to 63 VALUE logic 1 jitter<9:0> logic 0 logic 1 logic 0 logic 1 logic 0 logic 1 jitter<9:0> logic 0 intermediate start bit second sample of jitter word pause intermediate start bit assym<7:0> asymmetry word intermediate start bit pllfreq<9:0> PLL frequency word start bit jitter word FUNCTION
handbook, halfpage
bit 0 start bit
bit 1
bit 2
bit 3
MGR798
pause
data bits
Fig.8 Format on MEAS1 pin.
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21
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.5.3 PLL LOCK SELECT REGISTER (PLLLOCK)
SAA7392
The behaviour of this register is dependent upon whether its being read or written. The behaviour for the write operation is described in Tables 24 to 27. When read the 8 MSBs of the PLL frequency counter are returned; this is described in Tables 24 and 28. Table 24 PLL Lock Select Register (address 00H) - WRITE/READ 7 LockOride PLLFreq.7 6 PhaOset.2 PLLFreq.6 5 PhaOset.1 PLLFreq.5 4 PhaOset.0 PLLFreq.4 3 PLLFreq.3 2 PLLFreq.2 1 PLLFreq.1 0 PLLFreq.0
PLLForceL.3 PLLForceL.2 PLLForceL.1 PLLForceL.0
Table 25 Description of PLLLock bits for write operation BIT 7 SYMBOL LockOride DESCRIPTION When LockOride = 0, then automatic lock behaviour selected, PLLForceL<3:0> must be set to `0000'. When LockOride = 1, then PLL manual override, PLLForceL<3:0> must also be programmed. These 3 bits are used to select the phase override settings; see Table 26.
6 5 4 3 2 1 0
PhaOset.2 PhaOset.1 PhaOset.0
PLLForceL.3 These 4 bits are used to select the PLL lock; see Table 27. PLLForceL.2 PLLForceL.1 PLLForceL.0
Table 26 Selection of phase override setting PhaOset.2 0 0 0 0 1 1 1 1 PhaOset.1 0 0 1 1 0 0 1 1 PhaOset.0 0 1 0 1 0 1 0 1 reserved
3/ 2/ 1/ 8 8 8
PHASE OVERRIDE x PLL clock over-equalized T3 x PLL clock over-equalized T3 x PLL clock over-equalized T3 x PLL clock under-equalized T3 x PLL clock under-equalized T3 x PLL clock under-equalized T3
correct equalisation
1/ 2/ 3/ 8 8 8
Table 27 Selection of PLL lock PLLForceL.3 PLLForceL.2 PLLForceL.1 PLLForceL.0 0 0 0 0 1 X 2000 Mar 21 0 0 1 1 0 X 0 0 0 1 0 X 0 1 0 0 0 X 22 force PLL in-lock force PLL into outer-lock force PLL into inner-lock force PLL into Hold mode (PLL frequency can be forced using preset value in register PLLFreq) all other combinations are reserved PLL LOCK automatic lock behaviour
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
Table 28 Description of PLLock bits for read operation BIT 7 to 0 SYMBOL DESCRIPTION
SAA7392
PLLFreq<7:0> This register holds the 8 MSBs of the PLL frequency counter. The PLL frequency is calculated as shown below: ( PLLFreq<7:0> x ADC clock (Hz) ) f PLL (Hz) = ----------------------------------------------------------------------------------------128
7.5.4
PLL BANDWIDTH SELECT REGISTER (PLLSET)
The function of this register is dependent upon whether its being read or written. The function for the write operation is described in Tables 29 to 34. Note the measurement conditions are: system clock = 2.15 MHz, bit clock = 4.3 MHz, bandwidth is proportional to the system clock. When read this register returns the 8-bit PLL asymmetry value, see Table 29. Table 29 PLL Bandwidth Select Register (address 01H) - WRITE/READ 7 SliceBW.1 PLLAsym.7 6 SliceBW.0 PLLAsym.6 5 IntegF0.1 PLLAsym.5 4 IntegF0.0 PLLAsym.4 3 PLLBWF1.1 PLLAsym.3 2 PLLBWF1.0 PLLAsym.2 1 LPBWF2.1 PLLAsym.1 0 LPBWF2.0 PLLAsym.0
Table 30 Description of PLLSet bits for write operation BIT 7 6 5 4 3 2 1 0 SYMBOL SliceBW.1 SliceBW.0 IntegF0.1 IntegF0.0 PLLBWF1.1 These 2 bits select the PLL bandwidth; see Table 33. PLLBWF1.0 LPBWF2.1 LPBWF2.0 These 2 bits select the low-pass bandwidth; see Table 34. These 2 bits select the integrator crossover frequency; see Table 32. DESCRIPTION These 2 bits select the Slicer bandwidth; see Table 31.
Table 31 Selection of Slicer bandwidth SliceBW.1 0 0 1 1 SliceBW.0 0 1 0 1 12 Hz 50 Hz 200 Hz This value is reserved. SLICER BANDWIDTH
Table 32 Selection of integrator crossover frequency IntegFO.1 0 0 1 1 2000 Mar 21 IntegFO.0 0 1 0 1 3780 Hz 1890 Hz 945 Hz This value is reserved. 23 INTEGRATOR CROSSOVER FREQUENCY
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
Table 33 Selection of PLL bandwidth PLLBWF1.1 0 0 1 1 PLLBWF1.0 0 1 0 1 21000 Hz 10528 Hz 5264 Hz 2632 Hz PLL BANDWIDTH
SAA7392
Table 34 Selection of low-pass bandwidth LPBWF2.1 0 0 1 1 7.5.5 LPBWF2.0 0 1 0 1 42100 Hz 21000 Hz 10528 Hz This value is reserved. LOW-PASS BANDWIDTH
PLL FREQUENCY PRESET REGISTER (PLLFREQ)
The function of this register is dependent upon whether its being read or written. Tables 35 and 36 define the register function for the write operation. Tables 35 and 37 define the register function for the read operation. Table 35 PLL Frequency Preset Register (address 02H) - WRITE/READ 7 PLLFreq.9 JV.7 6 PLLFreq.8 JV.6 5 PLLFreq.7 JV.5 4 PLLFreq.6 JV.4 3 PLLFreq.5 JV.3 2 PLLFreq.4 JV.2 1 PLLFreq.3 JV.1 0 PLLFreq.2 JV.0
Table 36 Description of PLLFreq bits for write operation BIT 7 to 0 SYMBOL DESCRIPTION
PLLFreq<9:2> These are the 8 MSBs of the 10-bit code used to set the PLL frequency. The 2 LSBs reside in the PLLEqu register; these 2 bits should be written to first. The PLL frequency can be set using the following equation:
-5 PLLFreq<9:0> f PLL = ------------------------------------- + 2 x f clk 512
Table 37 Description of PLLFreq bits for read operation BIT 7 to 0 SYMBOL JV.7 to JV.0 DESCRIPTION Jitter value. These 8 bits determine the PLL clock jitter value (jitter values below 7% cannot be measured with this register). The absolute clock jitter value can be calculated as follows: PLL clock recovery jitter % = JV<7:0> - 6.5 ----------------------------------- x 100 2048
2000 Mar 21
24
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.5.6 PLL EQUALIZER PRESET REGISTER (PLLEQU)
SAA7392
The function of this register is dependent upon whether its being read or written. Tables 38, 39 and 40 define the register function for the write operation. Tables 38 and 41 define the register function for the read operation. Table 38 PLL Equalizer Preset Register (address 03H) - WRITE/READ 7 PLLFreq.1 - 6 PLLFreq.0 - 5 Tap a1.2 - 4 Tap a1.1 - 3 Tap a1.0 - 2 Tap a2.2 LongSymb 1 Tap a2.1 FLock 0 Tap a2.0 InLock
Table 39 Description of PLLEqu bits for write operation BIT 7 6 5 4 3 2 1 0 SYMBOL PLLFreq.1 PLLFreq.0 Tap a1.2 Tap a1.1 Tap a1.0 Tap a2.2 Tap a2.1 Tap a2.0 These 3 bits select the equalizer tap setting a2; see Table 40. These 3 bits select the equalizer tap setting a1; see Table 40. DESCRIPTION These 2 bits are the 2 LSBs of the 10-bit PLL frequency code; see Section 7.5.5.
Table 40 Selection of equalizer tap settings: a1 and a2 Tap a1.2 Tap a2.2 0 0 0 0 1 1 X Tap a1.1 Tap a2.1 0 0 1 1 0 0 X Tap a1.0 a1 OR a2 EQUALIZER TAP SETTINGS Tap a2.0 0 1 0 1 0 1 X 0 -0.0625 -0.125 -0.1875 -0.25 -0.3125 All other settings are reserved.
Table 41 Description of PLLEqu bits for read operation BIT 7 to 3 2 1 0 SYMBOL - LongSymb FLock InLock These 5 bits are reserved. If LongSymb = 1, then a run length of 14 has been detected. If FLock = 1, then PLL is in inner-lock range. If Inlock = 1, then PLL is in lock. DESCRIPTION
2000 Mar 21
25
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.5.7 PLL LOCK AID2 PRESET REGISTER (PLLFMEAS)
SAA7392
The PLL setting point for the EFM counting locking strategy is controlled by setting the PLL frequency such that, there are, on average, a fixed number of EFM transitions per PLL clock period: PLL Locking Frequency/EFM Transition Frequency = (EFM_Count + 32)/16 = 4.75 in a typical application. This value (4.75) is dependent on disc and mechanical variations, improvements may be achieved by adjusting the value slightly. Table 42 PLL Lock Aid2 Preset Register (address 04H) - WRITE 7 RL3_En 6 - 5 EFMns.5 4 EFMns.4 3 EFMns.3 2 EFMns.2 1 EFMns.1 0 EFMns.0
Table 43 Description of PLLFMeas bits BIT 7 6 5 to 0 SYMBOL RL3_En - EFMns<5:0> DESCRIPTION If RL3_En = 0, then EFM transition counting outer PLL lock strategy. If RL3_En = 1, then RL3 detection PLL outer lock strategy. This bit is reserved. These 6 bits select the EFM nominal setting. The default nominal setting should be set to `101110'.
7.5.8
MOTOR CONTROL REGISTER 2 (MOTOR2)
This is a dual-function register. When read Motor2 gives an indication of the EYE opening of the equalised HF. Table 44 Eye Open Register (address 0DH) - READ 7 EOV.7 6 EOV.6 5 EOV.5 4 EOV.4 3 EOV.3 2 EOV.2 1 EOV.1 0 EOV.0
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.5.9 VITERBI DETECTOR SETTING REGISTER (VITSET)
SAA7392
The Watchdog counter is a counter that counts on the front-end PLL clock. * If rl1 or a rl2 received: count + stepsize * Elsif no transition: count + 1 * Elsif transition on a valid runlength: count - 8 * Elsif (count > maxcount): reset count. Stepsize and maxcount can be set by writing to the VitSet register. On a reset of the counter the slice level is also reset.
This register controls an advanced data slicer for improved bit detector performance. * An adaptive slicer performs a second slice operation. This has a higher bandwidth than the first slicer. * If switched on, the run length 2 push-back circuit pushes all run length two symbols to run length 3. The circuit will determine which transition was most likely in error and shift transition on that edge. To avoid advanced detector hang-up, caused by a detection level that is too high and is not brought down, a Watchdog counter on the slicer level is installed.
Table 45 Viterbi Detector Setting Register (address 16H) - WRITE 7 AdSliceON 6 AdDetON 5 FEndAutoSON 4 RL2PB 3 WDog 2 MaxCnt 1 WDogCnt.1 0 WDogCnt.0
Table 46 Description of VitSet bits BIT 7 6 5 4 3 2 1 0 SYMBOL AdSliceON AdDetON FEndAutoSON RL2PB WDog MaxCnt WDogCnt.1 WDogCnt.0 DESCRIPTION If AdSliceON = 0, then slicer reset (to logic 0). If AdSliceON = 1, then slicer active. If AdDetON = 0, then advanced bit detector off. If AdDetON = 1, then advanced bit detector on. If FEndAutoSON = 0, then auto-scaling in front-end Hold mode. If FEndAutoSON = 1, then auto-scaling in front-end on. If RL2PB = 0, then run length 2 push-back off. If RL2PB = 1, then run length 2 push-back on. If WDog = 0, then slicer Watchdog is off. If WDog = 1, then slicer Watchdog is on. If MaxCnt = 0, then maxcount is 1024. If MaxCnt = 1, then maxcount is 2048. These 2 bits select the Watchdog count step; see Table 47.
Table 47 Selection of Watchdog count step WDogCnt.1 0 0 1 1 7.5.10 WDogCnt.0 0 1 0 1 MOTOR CONTROL REGISTER 1 (MOTOR1) WATCHDOG COUNT STEP 32 64 128 256
When read this register holds the 8-bit advanced slicer compensation value.
2000 Mar 21
27
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
Table 48 Motor Control Register 1 (address 0CH) - READ 7 ASCV.7 7.6 7.6.1 6 ASCV.6 5 ASCV.5 4 ASCV.4 3 ASCV.3 2 ASCV.2 1 ASCV.1
SAA7392
0 ASCV.0
Decoder function DEMODULATOR
7.6.2.1
CFLG pin
The demodulator block includes sync extraction, interpolation and protection circuits, and converts the 14-bit EFM data and subcode words into 8-bit symbols. Two counters are used to detect frame synchronisation. The coincidence counter detects the coincidence of successive syncs (i.e. 2 syncs are within 588 1 EFM clock). The main counter partitions the EFM signal into 16 or 17-bit bytes; and is reset when a sync coincidence is found or the sync pulse is within 6 EFM clock pulses. The sync coincidence signal generates the `lock' signal which goes active HIGH when one sync coincidence is found, and goes inactive when no sync coincidence is found within 61 consecutive EFM frames. The frame sync detection circuit extracts the frame sync and will guard against mis-detection; up to 7 consecutive corrupted syncs will not disturb the sync detection. After data demodulation the sector sync is extracted; a double lock counter is used. The main counter interpolates the sector syncs, and a coincidence counter resets the main counter. 7.6.2 ERROR CORRECTOR
The error corrector outputs status information in serial format on the CFLG pin. Each frame consists of 11 bits (each 7 system clock periods long), beginning with a start bit, then data bits then pause bit (see Fig.9). The repetition rate of CFLG is not fixed; it depends on the disc speed and output interface speed. There is always at least one pause bit. The structure of the frame is shown in Table 49. Table 49 Frame structure BIT 0 VALUE logic 1 start bit 000 = C1 correction 011 = C2 correction 100 = corrector not active all other codes not used 4 5 corfail flagfail failure flag set because correction impossible failure flag set because correction too risky COMMENT
1 to 3 cormode<2:0>
6 to 9 rootcount<3:0> number of errors corrected, after Euclidean algorithm 10 logic 0 pause bit
The error corrector can correct up to 2 errors on the C1 level and up to 4 errors on the C2 level. The error corrector also contains a flag processor. Flags are assigned to symbols when the error corrector cannot ascertain if the symbols are definitely good. C1 generates output flags that are used by C2. The C2 output flags are output via the FLAG signal along with the I2S, and can be used by the interpolator for concealment of uncorrectable errors for audio output. * Muting of data. Data output via the serial interface and/or the EBU can be set to zero using register Output3. * Concealment of audio errors. A simple 1 sample linear interpolator can be selected via register Output3. If selected the interpolator becomes active if a single sample is flagged as erroneous; left and right channels have independent interpolators.
handbook, halfpage
bit 0 start bit
bit 1
bit 2
bit 3
MGR798
pause
data bits
Fig.9 Format on CFLG pin.
2000 Mar 21
28
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.6.3 DECODER MODE SELECT REGISTER (DECOMODE)
SAA7392
Table 50 Decoder Mode Select Register (address 13H) - WRITE 7 Mode.6 6 Mode.5 5 Mode.4 4 Mode.3 3 Mode.2 2 Mode.1 1 Mode.0 0 LWCon
Table 51 Description of DecoMode bits BIT 7 to 1 0 SYMBOL Mode<6:0> LWCon DESCRIPTION These 7 bits select the Decoder mode; see Table 52. When a logic 0, LaserOn and WriteOn2 signals operate normally. When a logic 1, LaserOn and WriteOn2 signals are reset.
Table 52 Selection of Decoder mode MODE DECODER MODE 6 0 0 5 0 1 4 0 0 3 0 0 2 0 0 1 0 0 0 0 0 Flush mode. Deinterleaver table is emptied and all data is discarded. Normal play. Uses the Quad-pass error correction mode used for disc speeds up to 75% of maximum defined by ADCCLK. Note the data integrity should be checked using the CRC as the FLAG pin is not fully defined in this mode. Fast play. Used for audio play or fast CDROM mode (25 to 100% of maximum defined by ADCCLK), this reduces the error correction performance, but also halves the throughput time of error corrector (only dual pass error correction algorithm used). Hold mode. Data into output FIFO is stopped (header/subheader decoding remains operative). Encode mode. All other combinations reserved.
0
1
0
1
0
0
0
0 0 X 7.6.4
1 1 X
1 0 X
0 1 X
0 0 X
0 1 X
0 0 X
FRAME ERROR STATUS REGISTERS (C1BLER AND C2BLER)
These two registers are non-buffered counters. Each time a C1 frame with errors is found the register C1BLER is incremented. In the same way C2BLER increments on all C2 frames with errors. When the value of either register reaches 255, it will hold. When read, the register value is reset.
7.6.4.1
C1 Block Error Register (C1BLER)
Table 53 C1 Block Error Register (address 39H) - READ 7 C1BLER.7 6 C1BLER.6 5 C1BLER.5 4 C1BLER.4 3 C1BLER.3 2 C1BLER.2 1 C1BLER.1 0 C1BLER.0
7.6.4.2
C2 Block Error Register (C2BLER)
Table 54 C2 Block Error Register (address 3AH) - READ 7 C2BLER.7 6 C2BLER.6 5 C2BLER.5 4 C2BLER.4 3 C2BLER.3 2 C2BLER.2 1 C2BLER.1 0 C2BLER.0
2000 Mar 21
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.6.5 DATA FIFO
SAA7392
7.6.5.4 Data FIFO monitoring
The decoder block can be viewed as a FIFO, demodulated data is written in while the output interface reads from it. The way in which the FIFO is filled depends on the decoder mode set via register DecoMode. The decoder modes that effect the filling of the FIFO are described in Sections 7.6.5.1 to 7.6.5.3. Data is read out via the output interface and is only possible if enough data is present in the FIFO. The minimum amount of data is 110 C1 frames (C1 frame = 24 user bytes).
The state of the internal data FIFO may be monitored by reading the AnaSet1 register. This gives the number of C1 frames present in the FIFO including those frames in the outer corrector (i.e. 110 in CD fast and 220 in CD normal). One C1 frame equates to 24 user bytes in CD mode). 7.7 Subcode interface
7.6.5.1
Flush mode
The FIFO content is thrown away; no read-out possible. It is necessary to flush the FIFO every time a context switch is made; when data written to the FIFO is not subsequent with data already present in the FIFO.
Q-channel subcode data can be read using the ClockPre and DecoMode registers. The ClockPre register must be read first; this contains the status of the Q-channel subcode that may be read. Reading the ClockPre register with Ready = 1 will block the subcode interface for data read; no new subcode will overwrite the current subcode, and the microprocessor may retrieve as many bytes (up to 12) as required by issuing reads to register DecoMode. After finishing the subcode read the microprocessor must release the interface by issuing a read to the dummy register SubReadEnd (no data can be read from it); this allows the SAA7392 to capture new subcode frames. The serial Q to W subcode is output on the V4 pin as illustrated in Fig.10. The subcode sync word is formed by a pause of 200/n s minimum; where n = the disc speed. Each subcode word starts with a logic 1 followed by 7 bits (Q to W); the bit time is 0.5 of the period of the WCLK signal, (11.3/n s). The gap between the words is between 11.3/ and 90/ s. Note that the subcode data cannot be n n guaranteed at a rate higher than 0.5 x the maximum data rate programmed. The subcode data is also available in the EBU output (EBUOUT).
7.6.5.2
Hold mode
Writing to the FIFO is stopped; read-out possible if FIFO was filled. This mode is intended to avoid FIFO overflow by implementing a `stop write - jump back' action in the microprocessor. When the microprocessor switches to hold mode the switch-over is synchronised internally with the next subcode block start, allowing the microprocessor to know exactly where the writing will stop or start. This mode is also intended to avoid overflow in the block decoder; on imminent overflow the microprocessor can switch to hold mode. When it jumps back one track and switches off hold mode on the same subcode address the SAA7392 will make a seamless link.
7.6.5.3
Play mode
The FIFO is filled; read-out possible when FIFO filling big enough.
handbook, full pagewidth
200/n s min
11.3/n s
11.3/n s min 90/n s max
W96
1
Q1
R1
S1
T
U1
V
W1
1
Q2
MGR799
n = disc speed
Fig.10 Subcode format and timing on V4 pin.
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.7.1 CLOCK PRESET REGISTER (CLOCKPRE)
SAA7392
This is a dual-function register. When read the status of the Q-channel is returned. Table 55 Clock Preset Register (address 12H) - READ 7 Ready 6 Busy 5 CRC OK 4 - 3 - 2 - 1 - 0 -
Table 56 Description of ClockPre bits BIT 7 6 5 4 to 0 7.7.2 SYMBOL Ready Busy CRC OK - DESCRIPTION If Ready = 0, then buffer filling. If Ready = 1, then valid Q subcode frame available. If Busy = 0, then buffer filling. If Busy = 1, then buffer held (set after reading this register with Ready = 1). If CRC OK = 0, then CRC not checked or not OK. If CRC OK = 1, then CRC of Q-channel checks OK, only valid if Ready = 1. These 5 bits are reserved.
DECODER MODE SELECT REGISTER (DECOMODE)
This is a dual-function register. When read this register holds the Q-channel subcode data. Table 57 Decoder Mode Select Register (address 13H) - READ 7 SubD.7 7.7.3 6 SubD.6 5 SubD.5 4 SubD.4 3 SubD.3 2 SubD.2 1 SubD.1 0 SubD.0
SUBCODE READ END REGISTER (SUBREADEND)
After finishing a subcode read, the microprocessor must release the interface to allow the SAA7392 to capture new subcode frames. This is done by issuing a read to SubReadEnd. No data can be read from this register; only the side effect is important. Table 58 Subcode Read End Register (address 14H) - READ 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 -
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.8 Digital output
SAA7392
The EBU interface uses a clock derived from XTLI for timing generation. For correct operation of the EBU interface, BCLK must be non-gated and the selected EBU clock and BCLK must fulfil the following constraint: EBU clock = WCLK x 64 WCLK is BCLK divided by 16, 24 or 32 depending on the chosen output format.
The AES/EBU signal is available on pin EBUOUT, according to the format defined by the "IEC958 specification". This signal is only available in the CLV modes of the decoder (not in QCLV). Three different modes can be selected: * EBU off * EBU data all zero * EBU data valid. 7.8.1 INPUT CONFIGURATION REGISTER (INPUTCONFIG)
Table 59 Input Configuration Register (address 1EH) - WRITE 7 EBUClkSelect 6 - 5 - 4 - 3 - 2 ScramOn 1 InputFmt.1 0 InputFmt.0
Table 60 Description of InputConfig bits BIT 7 SYMBOL EBUClkSelect DESCRIPTION If EBUClkSelect = 0, then the EBU clock frequency is 1/3fXTLI. If EBUClkSelect = 1, then the EBU clock frequency is 2/3fXTLI (input MUXSWI must be a logic 1 for this setting). These 4 bits are reserved. See Section 7.11.1.
6 to 3 2 1 0
- ScramOn InputFmt1 InputFmt0
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.8.2 FORMAT
SAA7392
The digital audio output consists of 32-bit words (subframes) transmitted in biphasemark code (two transitions for a logic 1 and one transition for a logic 0). Words are transmitted in blocks of 384. Table 61 Digital audio output subframe format BIT 0 to 3 FIELD NAME sync DESCRIPTION The sync word is formed by violation of the biphase rule and therefore does not contain any data. Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations: * Sync B: Start of a block (384 words), word contains left sample * Sync M: Word contains left sample (no block start) * Sync W: Word contains right sample. 4 to 7 8 to 27 28 29 30 auxiliary audio sample validity flag user data channel status These bits are not used; normally zero. Left and right samples are transmitted alternately. The first 4 bits not used (always zero); 2's compliment; LSB = bit 12 and MSB = bit 27. If validity flag = 1, audio samples are flagged if an error has been detected but was uncorrectable. This flag remains the same even if data is taken after concealment. Subcode bits Q until W from the subcode section are transmitted via the user data bit. This data is asynchronous with the block rate. The channel status bit is the same for left and right words. Therefore, a block of 384 words contains 192 channel status bits. The category code is always CD. The bit assignment is shown in Table 62. Even parity for bits 4 to 30.
31
parity bit
Table 62 Channel status bit assignment BIT 0 to 4 5 to 7 8 to 15 28 to 29 FIELD NAME control reserved mode category code clock accuracy DESCRIPTION Bits 1 to 4 copied from register Output2. Bit 2 is logic 1 when copy permitted. Bit 3 is logic 1 when recording has pre-emphasis always zero CD: bit 8 = logic 1, all other bits = logic 0 set by register Output2: 10 = level I 00 = level II 01 = level III 16 to 27, 30 to 191 remaining always zero
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.9 Serial output interface
SAA7392
The BCLK frequency can be selected by register ClockPre, or input externally. If the data out rate does not correspond with the disc speed and the bit clock data, the FIFO will either fill or empty. FIFO underflow (STOPCK output goes HIGH indicating absence of data) must be avoided. If BCLK is an input, it should be stopped and restarted again when STOPCK goes LOW. If BCLK is output, it is automatically stopped if BCLK gate enable is set (via register ClockPre); if it is not set then unpredictable operation will result.
The serial data output interface consists of three signals: WCLK (word select), BCLK (serial clock), DATAO (serial data). The polarity of WCLK and the data can be inverted. The FLAG signal is used to identify if there are errors in either the LSB or MSB of the 16-bit data word. The interface can be used as a master or slave interface (BCLK and WCLK are then inputs), selectable by register Output1. The serial data interface can be switched into two modes: Philips I2S and the EIAJ format (the protocol can use either 16, 24 or 32 BCLK clocks for each 16-bit output, selectable by Output1 register). The formats are shown in Figs 11 to 16.
handbook, full pagewidth
BCLK
DATA
D1
D0 D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 D15 D14
FLAG
FLAG - MSB (1 is unreliable)
FLAG - LSB
WCLK
left
right
SYNC
MGR800
Fig.11 Format 1: 16 clocks/word I2S format.
handbook, full pagewidth
BCLK
DATA
D1
D0 D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 D15 D14
FLAG
FLAG - MSB (1 is unreliable)
FLAG - LSB
WCLK
right
left
SYNC
MGR801
Fig.12 Format 2: 16 clocks/word `S' format (WCLK inverted).
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
handbook, full pagewidth BCLK
DATA
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
FLAG
FLAG - MSB (1 is unreliable)
FLAG - LSB
WCLK
left
right
SYNC
MGR802
Fig.13 Format 3: 24 clocks/word I2S format.
handbook, full pagewidth BCLK
DATA
D1
D0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FLAG
FLAG - MSB (1 is unreliable)
FLAG - LSB
WCLK
right
left
SYNC
MGR803
Fig.14 Format 4: 24 clocks/word `S' format (WCLK inverted).
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BCLK DATA
D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Philips Semiconductors
Channel encoder/decoder CDR60
BCLK
DATA
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
FLAG
FLAG - MSB (1 is unreliable)
FLAG - LSB
WCLK
left
right
SYNC
MGR804
Fig.15 Format 5: 32 clocks/word I2S format.
FLAG
FLAG - MSB (1 is unreliable)
FLAG - LSB
WCLK
right
left
Preliminary specification
SYNC
SAA7392
MGR805
Fig.16 Format 6: 32 clocks/word `S' format (WCLK inverted).
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.9.1 I2S OUTPUT REGISTER (OUTPUT1)
SAA7392
Table 63 I2S Output Register 1 (address 05H) - WRITE 7 Format.2 6 Format.1 5 Format.0 4 WClkIO 3 BClkIO 2 - 1 - 0 -
Table 64 Description of Output1 bits BIT 7 6 5 4 3 2 to 0 SYMBOL Format.2 Format.1 Format.0 WClkIO BClkIO - When WClkIO = 0, then WCLK is in Input mode. When WClkIO = 1, then WCLK is in Output mode. When BClkIO = 0, then BCLK is in Input mode. When BClkIO = 1, then BCLK is in Output mode. These 3 bits are reserved. DESCRIPTION These 3 bits select the format; see Table 65.
Table 65 Format selection Format.2 0 0 0 0 1 1 7.9.2 Format.1 0 0 1 1 0 0 Format.0 0 1 0 1 0 1 FORMAT Format 1 Format 2 Format 3 Format 4 Format 5 Format 6
I2S OUTPUT REGISTER 2 (OUTPUT2)
Table 66 I2S Output Register 2 (address 06H) - WRITE 7 EBUValid 6 EBUOn 5 EBUCon.29 4 EBUCon.28 3 EBUCon.3 2 EBUCon.2 1 EBUCon.1 0 EBUCon.0
Table 67 Description of Output2 bits BIT 7 6 5 4 3 to 0 SYMBOL EBUValid EBUOn EBUCon.29 EBUCon.28 EBUCon<3:0> DESCRIPTION If EBUValid = 0, then EBU/IEC958 output data zero. If EBUValid = 1, then EBU/IEC958 output data valid. If EBUOn = 0, then EBU/IEC958 output is switched off. If EBUOn = 1, then EBU/IEC958 output switched on. These 2 bits are copied to bits 29 and 28 of the IEC958 control channel (crystal accuracy); see Table 62. These 4 bits are copied to bits 4 to 1 of the IEC958 control channel (data/audio, copy protect, de-emphasis); see Table 62.
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.9.3 I2S OUTPUT REGISTER 3 (OUTPUT3)
SAA7392
Table 68 I2S Output Register 3 (address 07H) - WRITE 7 WClkHLeft 6 DescrmOn 5 InterpOn 4 - 3 FlagPin 2 KillDataOn 1 KillEBUOn 0 -
Table 69 Description of Output3 bits BIT 7 SYMBOL WClkHLeft DESCRIPTION When WClkHLeft = 0, then WCLK is HIGH on right byte of I2S/S format output; (use for I2S format modes). When WCLKHLeft = 1, then WCLK is HIGH on left byte of I2S/S format output; (use for S format modes). When DescrmOn = 1, then Descrambling function on. For CD-DA playback descrambling has to be switched off. For CD-ROM descrambling is required but it might also be possible that a descrambling function is available in the buffer manager (block decoder). 5 4 3 2 1 0 InterpOn - FlagPin KillDataOn KillEBUOn - When InterpOn = 0, then audio data interpolation is switched off. When InterpOn = 1, then audio data interpolation switched on. This bit is reserved. When FlagPin = 0, then flag pin sends out EDC-OK signal on byte 2063 of the sector. When FlagPin = 1, then flag pin sends out reliability flag information. When KillDataOn = 0, then in normal mode. When KillDataOn = 1, then all data in serial output channel is set to zero. When KillEBUOn = 0, then in normal mode. When KillEBUOn = 1, then all data in IEC958/EBU channel is set to zero This bit is reserved.
6
DescrmOn
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.10 Motor control
SAA7392
The spindle motor is controlled by a fully integrated digital servo sub-system within the SAA7392. Information from the data FIFO, data recovery PLL and tacho inputs may be used to calculate the motor control output signals. The frequency set-point, the FIFO settings and coefficients G, Ki and Kf are all programmable using the seven motor control registers. The motor can be controlled in either Pulse Width Mode (PWM) or Pulse Density Mode (PDM). The tacho control subsystem allows a range of different motor tacho systems to be used, the modes and prescalers are programmable via the tacho register set. (Note due to pin multiplexing, PWM motor control mode and CAV mode using tacho control are mutually exclusive).
handbook, full pagewidth T1
T2 MOTO2/T3
TRANSITION DETECTOR K tacho
TACHO LOW-PASS FILTER
tacho frequency
COMPARE tacho interrupt
frequency/tacho set-point
tacho set-point 1/(2.667 x system clock)
overflow detector
-
Wobble frequency PLL frequency
+
+
+ +
24T
G
PDM/PWM MODULATOR
motor pads
SW1 FIFO half-full set-point
Ki SW2
analog output stage gain
M
-
FIFO filling
+
+
reset Kf GE
motor EXTERNAL MOTOR CIRCUIT
MGR807
XError
Fig.17 Motor servo block diagram.
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.10.1 MOTOR CONTROL REGISTER 1 (MOTOR1)
SAA7392
The frequency/tacho set-point (i.e. the target PLL or tacho frequency) is calculated as follows: MFS<7:0> Frequency set-point = 1 - --------------------------- x 2.667 x ADC clock 256 PLLFreqR<7:0> PLL frequency = ----------------------------------------- x ADC clock - 128 Note that: (PLL frequency - frequency set-point) must be less than 1.33 x ADC clock. Table 70 Motor Control Register 1 (address 0CH) - WRITE 7 MFS.7 7.10.2 6 MFS.6 5 MFS.5 4 MFS.4 3 MFS.3 2 MFS.2 1 MFS.1 0 MFS.0
MOTOR CONTROL REGISTER 2 (MOTOR2)
Table 71 Motor Control Register 2 (address 0DH) - WRITE 7 G.2 6 G.1 5 G.0 4 Ki.1 3 Ki.0 2 Kf.2 1 Kf.1 0 Kf.0
Table 72 Description of Motor2 bits BIT 7 6 5 4 3 SYMBOL G.2 G.1 G.0 Ki.1 Ki.0 These 2 bits select coefficient Ki; see Table 74. In order to set the integrator bandwidth low enough at high system clock speeds, an extra divider for Ki has been added. This is set by writing to register Motor7. The resulting Ki(tot) is then the Ki set by Motor2 multiplied by the Ki' set by Motor7. These 3 bits select coefficient Kf; see Table 75. DESCRIPTION These 3 bits select coefficient G; see Table 73.
2 1 0
Kf.2 Kf.1 Kf.0
Table 73 Selection of coefficient G G.2 0 0 0 0 1 1 1 1 G.1 0 0 1 1 0 0 1 1 G.0 0 1 0 1 0 1 0 1 8.36 10.4 16.7 20.9 33.4 41.8 66.9 83.6 COEFFICIENT G
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
Table 74 Selection of coefficient Ki Ki.1 0 0 1 1 Ki.0 0 1 0 1 3.1 x 10-5 6.1 x 10-5 1.2 x 10-4 2.4 x 10-4 COEFFICIENT Ki
SAA7392
Table 75 Selection of the coefficient Kf Kf.2 0 0 0 0 1 1 1 1 7.10.3 Kf.1 0 0 1 1 0 0 1 1 Kf.0 0 1 0 1 0 1 0 1 reserved 3.7 x 10-9 7.5 x 10-9 1.5 x 10-8 3.0 x 10-8 6.0 x 10-8 1.2 x 10-7 2.4 x 10-7 COEFFICIENT Kf
MOTOR CONTROL REGISTER 7 (MOTOR7)
Table 76 Motor Control Register 7 (address 1DH) - WRITE 7 PhErSrc 6 - 5 Kf'.2 4 Kf'.1 3 Kf'.0 2 Ki'.2 1 Ki'.1 0 Ki'.0
Table 77 Description of Motor7 bits BIT 7 6 5 4 3 SYMBOL PhErSrc - Kf'.2 Kf'.1 Kf'.0 DESCRIPTION If PhErSrc = 0, then the phase error source is FIFOFil. If PhErSrc = 1, then the phase error source is XError. This bit is reserved. These 3 bits select the value of the Kf' coefficient; see Table 78. Kf' operates by sampling the input. For example, for Kf' = 1, every sample of the input is passed through to a following integrator circuit, for a Kf' of 0.5 every 2nd sample is passed through, for a Kf' of 0.25 every 4th sample is passed through, and so on. For a DC input signal, Kf x Kf' should always give the same result. If however, the input is varying sufficiently quickly, the Kf x Kf' combinations with the same product will not always give the same result, especially for low values of Kf', where the sampling in the extreme becomes 1 out of every 128 samples. (The input samples to the block that performs the Kf' multiplication occur at a rate of 1 sample every 24 system clock periods.) 2 1 0 Ki'.2 Ki'.1 Ki'.0 These 3 bits select the value of the Ki' coefficient; see Table 78.
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
Table 78 Selection of coefficient Kf' and Ki' Kf'.2 Ki'.2 0 0 0 0 1 1 1 1 7.10.4 Kf'.1 Ki'.1 0 0 1 1 0 0 1 1 Kf'.0 Ki'.0 0 1 0 1 0 1 0 1 1 0.5 0.25 0.125 0.0625 0.03125 0.015625 0.0078125 COEFFICIENTS Kf' AND Ki'
SAA7392
MOTOR CONTROL REGISTER 3 (MOTOR3)
The function of this register is dependent upon whether its being read or written. When written, the value determines the FIFO set-point value in C1 frames (one C1 frame is 24 bytes). The FIFO set-point value should be set to a value greater than 110 frames for CD Fast mode and greater than 219 frames for CD Normal mode. The maximum value for the FIFO half-full value is 256. Normally, the FIFO set-point value should be set to the minimum value plus a margin for disc overspeed. The set-point value is calculated as shown below: FIFO set-point value = HFSP<7:0> x 8. When read, the motor speed can be determined from the recovered tacho frequency. Note this information is only valid when a Hall motor is being used in the application and the tacho subsystem is correctly configured. The reading is related to the motor frequency (relative to pulse rate on a single tacho input pin) as shown in Equation (1); the actual Tacho frequency can be calculated as shown in Equation (2). Negative frequencies will be measured if the motor is rotating in reverse. [ ( 6 x Tacho1 ) x Motor frequency ] Tacho4 = ---------------------------------------------------------------------------------------(1) Tacho sample rate ADC clock Tacho frequency (Hz) = Tacho4 x --------------------------128 Table 79 Motor Control Register 3 (address 0EH) - WRITE/READ 7 HFSP.7 TachoFreq.7 6 HFSP.6 TachoFreq.6 5 HFSP.5 TachoFreq.5 4 HFSP.4 TachoFreq.4 3 HFSP.3 TachoFreq.3 2 HFSP.2 TachoFreq.2 1 HFSP.1 TachoFreq.1 0 HFSP.0 TachoFreq.0 (2)
Table 80 Description of Tacho4 bits for read operation BIT 7 to 0 SYMBOL TachoFreq<7:0> DESCRIPTION These 8 bits indicate the Tacho frequency (2's complement notation).
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.10.5 MOTOR CONTROL REGISTER 4 (MOTOR4)
SAA7392
Table 81 Motor Control Register (address 0FH) - WRITE 7 PWM_PDM 6 OVF_SW 5 SW1 4 SW2 3 MSCON.3 2 MSCON.2 1 MSCON.1 0 MSCON.0
Table 82 Description of Motor4 bits BIT 7 6 5 4 3 2 1 0 SYMBOL PWM_PDM OVF_SW SW1 SW2 MSCON.3 MSCON.2 MSCON.1 MSCON.0 DESCRIPTION If PWM_PDM = 0, then motor control in PWM mode. If PWM_PDM = 1, then motor control in PDM mode. If OVF_SW = 0, then SW1 and SW2 in normal operation. If OVF_SW = 1, then SW1 and SW2 will both open on overflow. If SW1 = 0, then SW1 is open. If SW1 = 1, then SW1 is closed. If SW2 = 0, then SW2 is open. If SW2 = 1, then SW2 is closed. These 4 bits are used to select the motor servo state; see Table 83.
Table 83 Selection of motor servo state MSCON.3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MSCON.2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MSCON.1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MSCON.0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Motor start at 37% power. Motor start at 50% power. Motor start at 75% power. Motor start at 100% power. Motor stop at 37% power. Motor stop at 50% power. Motor stop at 75% power. Motor stop at 100% power. MOTOR SERVO STATE Motor servo active. Motor servo off (clears integrator). Motor servo 3-state (motor output pin 3-states). These 5 codes are reserved.
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.10.6 MOTOR CONTROL REGISTERS 5 AND 6
SAA7392
These two registers hold the 16-bit motor integrator value. The motor integrator value can be read or updated using registers Motor5 and Motor6. Register Motor5 should be read or written first to prevent spurious results.
7.10.6.1
Motor Control Register 5 (Motor5)
Table 84 Motor Control Register 5 (address 10H) - READ/WRITE 7 MIV.7 6 MIV.6 5 MIV.5 4 MIV.4 3 MIV.3 2 MIV.2 1 MIV.1 0 MIV.0
7.10.6.2
Motor Control Register 6 (Motor6)
Table 85 Motor Control Register 6 (address 11H) - READ/WRITE 7 MIV.15 7.10.7 6 MIV.14 5 MIV.13 4 MIV.12 3 MIV.11 2 MIV.10 1 MIV.9 0 MIV.8
TACHO GAIN SETTING REGISTER (TACHO1)
This register holds the 8-bit Tacho multiplier frequency value. Table 86 Tacho Gain Setting Register (address 17H) - WRITE 7 KTacho.7 7.10.8 6 KTacho.6 5 KTacho.5 4 KTacho.4 3 KTacho.3 2 KTacho.2 1 KTacho.1 0 KTacho.0
TACHO TRIP SETTING REGISTER (TACHO2)
This register holds the 8-bit Tacho interrupt trip frequency value. Table 87 Tacho Trip Setting Register (address 18H) - WRITE 7 TIntF.7 6 TIntF.6 5 TIntF.5 4 TIntF.4 3 TIntF.3 2 TIntF.2 1 TIntF.1 0 TIntF.0
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.10.9 TACHO CONTROL REGISTER 3 (TACHO3)
SAA7392
Table 88 Tacho Control Register 3 (address 19H) - WRITE 7 SConS.1 6 SConS.0 5 TachoFRes 4 Moto2/T3 3 Fsam.1 2 Fsam.0 1 TachoIntLF 0 TachoMode
Table 89 Description of Tacho3 bits BIT 7 6 5 4 3 2 SYMBOL SConS.1 SConS.0 TachoFRes Moto2/T3 Fsam.1 Fsam.0 If TachoFRes = 0, then the tacho filter is enabled (normal mode). If TachoFRes = 1, then the tacho filter is reset. If Moto2/T3 = 0, then MOTO2 pin is an output. If Moto2/T3 = 1, then MOTO2 pin is tacho T3. These 2 bits select the tacho sample rate (fs) as shown below: 2 x Fsam<1:0> x system clock f s ( Hz ) = ---------------------------------------------------------------------------------32768 If TacholntLF = 0, then tacho interrupt is enabled on frequencies LOWER than set-point. If TacholntLF = 1, then tacho interrupt is enabled on frequencies HIGHER than set-point. If TachoMode = 0, tacho is in 3-pin mode. If TachoMode = 1, tacho is in 1-pin mode.
2
DESCRIPTION These 2 bits select the motor servo frequency source; see Table 90.
1
TachoIntLF
0
TachoMode
Table 90 Motor servo frequency source selection SConS.1 0 0 1 1 SConS.0 0 1 0 1 This value is reserved. Motor servo runs on tacho frequency. This value is reserved. MOTOR SERVO FREQUENCY SOURCE Motor servo locks to PLL clock (recovered from channel EFM).
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.11 The serial in function
SAA7392
The serial in function takes serial data from the block decoder and passes the data on to the encoder. It supports the I2S and Sony 3-wire serial interfaces (DATAI, BCLK and WCLK). The block is slave to the interface and therefore the BCLK and WCLK signals are generated externally and are the same signals as the serial data output interface. The selection of the input format follows the output interface setting. 7.11.1 INPUT CONFIGURATION REGISTER (INPUTCONFIG)
Table 91 Input Configuration Register (address 1EH) - WRITE 7 EBUClkSelect 6 - 5 - 4 - 3 - 2 ScramOn 1 InputFmt.1 0 InputFmt.0
Table 92 Description of InputConfig bits BIT 7 6 to 3 2 SYMBOL EBUClkSelect See Section 7.8.1. - ScramOn These 4 bits are reserved. This bit enables/disables the scrambling function. If ScramOn = 1, then the scrambling function is enabled. Scrambling must be off for CD-DA and on for CD-ROM. However, if the buffer manager (block decoder) already scrambles the CD-ROM data, then the user must switch scrambling off in the CDR60. 1 0 InputFmt.1 InputFmt.0 These 2 bits select the input format to the encoder; see Table 93. DESCRIPTION
Table 93 Selection of encoder input format INPUTFMT.1 0 0 1 INPUTFMT.0 0 1 X normal input data to encoder all zero input data to encoder random input data to encoder INPUT FORMAT
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Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.12 The subcode insert function
SAA7392
It is possible to begin subcode recording at any point in the subcode frame, for both internally and externally generated subcode, by loading the preset count field (bits PCF<6:0> in the SubPresetCount register) with the start position in the subcode frame and setting the init_frame bit to a logic 1. It must be ensured that, if used, the external block encoder is ready to transmit subcode data before the frame initialisation is started. When the frame initialisation sequence is complete the init_frame bit is automatically cleared to a logic 0. It should be noted that the frame initialisation sequence must be carried out at the beginning of every record session, even if starting from byte 0.
The SAA7392 allows two modes of subcode insertion: Bypass mode and Auto-format mode. * Bypass mode. In this mode the subcode is generated by a block decoder (such as PLUM) and transmitted to the SAA7392 via the proprietary Subcode Record Interface (SRI). P, Q and R to W channels are supported in this mode. However, the Q-channel CRC and the S0 and S1 bytes are generated by the SAA7392. The Q-channel CRC is calculated from the SRI data Q-bits and hence the 16 Q-channel CRC bits in the SRI data are discarded. * Auto-format mode. In this mode, the SAA7392 will generate subcode data itself. However, only P and Q subcode channels are supported. 7.12.1
SUBCODE PRESET COUNT REGISTER (SUBPRESETCOUNT)
The preset count field is loaded when this register is written. The current count field is returned when this register is read. Table 94 Subcode Preset Count Register (address 22H) - WRITE 7 init_frame 6 PCF.6 5 PCF.5 4 PCF.4 3 PCF.3 2 PCF.2 1 PCF.1 0 PCF.0
Table 95 Subcode Preset Count Register (address 22H) - READ 7 init_frame 6 CCF.6 5 CCF.5 4 CCF.4 3 CCF.3 2 CCF.2 1 CCF.1 0 CCF.0
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Channel encoder/decoder CDR60
7.12.2 SUBCODE CONFIGURATION REGISTER 1 (SUBCONFIG1)
SAA7392
Table 96 Subcode Configuration Register 1 (address 23H) - WRITE 7 sri_on 6 p_toggle 5 p_one 4 time1 3 time2 2 copy_alter 1 zero_inc 0 time3
Table 97 Description of SubConfig1 bits BIT 7 SYMBOL sri_on DESCRIPTION If sri_on = 0, then subcode generated by CDR60 for P and Q-channels; R to W channels are all logic 0's. If sri_on = 1, then subcode data from SRI except Q-channel CRC and S0 and S1 bytes. SRI frame sync checking is enabled. SubConfig1 register bits 1 to 6 do not effect the SRI subcode data. If p_toggle = 0, then P-channel takes value of the p_one bit. If p_toggle = 1, then P-channel is the value of bit 5 of the absolute frame byte in the current Q-code memory bank. P-channel is the value of this bit. The P-channel takes on a new value of p_one at the start of a subcode frame. These 3 bits control the incrementing and decrementing of the Q-channel absolute and relative time fields; see Table 98.
6
p_toggle
5 4 3 0 2
p_one time1 time2 time3 copy_alter
If copy_alter = 0, then the copy bit will hold its current value. The copy bit value can be changed by writing to the Q-code memory control byte via the SubData register. If copy_alter = 1, then the copy bit in the subcode control byte will alternate every 4 subcode frames. This is accomplished by copying bit 2 of the current Q-code memory absolute frame byte to the copy bit of the Q-code memory control byte. If zero_inc = 0, then all bits of the Q-code memory zero byte will hold. If zero_inc = 1, then bits 0 to 3 of the current Q-code memory zero byte are incremented modulo 10. Bits 4 to 7 are unchanged.
1
zero_inc
Table 98 Selection of Q-channel time fields time3 0 0 1 1 1 X time2 0 1 0 0 1 X time1 0 1 0 1 1 X Q-CHANNEL TIME FIELD increment relative and absolute time increment relative time and hold absolute time hold relative time and increment absolute time decrement relative time and increment absolute time hold relative and absolute time All other settings are reserved.
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Preliminary specification
Channel encoder/decoder CDR60
7.12.3 SUBCODE CONFIGURATION REGISTER 2 (SUBCONFIG2)
SAA7392
Table 99 Subcode Configuration Register 2 (address 24H) - READ/WRITE 7 BSwOn 6 InOBO 5 relcnt.2 4 relcnt.1 3 relcnt.0 2 curcnt.2 1 curcnt.1 0 curcnt.0
Table 100 Description of SubConfig2 bits BIT 7 6 SYMBOL BSwOn InOBO DESCRIPTION If BSwOn = 0, then no bank switching. If BSwOn = 1, then bank switch will occur when first subcode sync output by EFM modulator and curcnt<2:0> = 000 If InOBO = 0, then original bank is used again. In this case no bank switching or interrupts occur and automatic bank update is still done on the original bank, even when the other bank is output. If InOBO = 1, then the other bank is automatically inserted once into Q-channel, this bit is automatically reset to logic 0. Count value to load curcnt<2:0>. Current value of subcode frame counter.
5 to 3 2 to 0 7.12.4
relcnt<2:0> curcnt<2:0>
SUBCODE START DATA REGISTER (SUBSTARTDATA)
Table 101 Subcode Start Data Register (address 25H) - WRITE 7 NextSet 6 - 5 - 4 - 3 - 2 - 1 - 0 -
Table 102 Description of SubStartData bits BIT 7 6 to 0 7.12.5 SYMBOL NextSet - DESCRIPTION If NextSet = 0, then access other bank. If NextSet = 1, then access current bank that is being used for Q-channel data. These 7 bits are reserved.
SUBCODE DATA REGISTER (SUBDATA)
Sub-CPU read/write from/to the SubData register causes a read or write to occur on the Q-code memory. Normally the sub-CPU would access all 10 bytes of a Q-code bank. Before such a block access the sub-CPU must issue a write to the SubStartWrite register. Table 103 Subcode Data Register (address 26H) - READ/WRITE 7 QCD.7 6 QCD.6 5 QCD.5 4 QCD.4 3 QCD.3 2 QCD.2 1 QCD.1 0 QCD.0
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Channel encoder/decoder CDR60
7.12.6 GENERATING CD-TEXT 7.13 The data encoder block
SAA7392
CD-Text is stored in the R to W channels of the disc. The CD-Text standard states that a CD-Text disc must at least contain CD-Text information in the lead-in, and it may contain CD-Text information in the program area. CDR60 supports writing of the R to W subcode channels only in bypass mode which means that the whole subcode information has to be generated from an external device. It is not possible to use the automatic subcode formatting features like auto-incrementing or the two buffers which means that the application has to take care of the whole subcode formatting itself. However, if an application likes to write a CD-Text disc that contains CD-Text information only in the lead-in area, then the application can use the auto-format features for writing the program area and only use the bypass mode to write CD-Text information when writing the lead-in. 7.14.1
This block generates all C1/C2 error correction data for the raw data. 7.14 Encode control block
This block controls the starting and stopping of the writing process. It does this based on the QSync signal it receives from the subcode insert block and the ATIPSync and W441 disc position information it receives from the Wobble processor.
ENCODE WRITEON CONTROL REGISTER (ENCODEWCON)
Table 104 Encode WriteOn Control Register (address 30H) - READ/WRITE 7 WriteOn1 6 WriteOn2 5 EFMDelOn 4 Count.4 3 Count.3 2 Count.2 1 Count.1 0 Count.0
Table 105 Description of EncodeWContr bits BIT 7 6 5 SYMBOL WriteOn1 WriteOn2 EFMDelOn DESCRIPTION If WriteOn1 = 0, then laser is off or turn laser off. If WriteOn1 = 1, then laser is on or turn laser on. If WriteOn2 = 0, then data flow is off or turn data flow off. If WriteOn2 = 1, then data flow is on or turn data flow on. If EFMDelOn = 0, then disable delay of WriteOn1. If EFMDelOn = 1, then enable delay of WriteOn1 with EncodeStartOffset/EncodeStopOffset of W441 pulses relative to ATIPSync. These 5 bits determine the delay generation of internal WriteOn flags by Count<4:0> ATIPSyncs.
4 3 2 1 0
Count.4 Count.3 Count.2 Count.1 Count.0
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Channel encoder/decoder CDR60
7.14.2 ENCODE START OFFSET REGISTER (ENCODESTARTOFFSET)
SAA7392
Table 106 Encode Start Offset Register (address 31H) - WRITE 7 6 5 4 3 2 1 0
StartOffset.7 StartOffset.6 StartOffset.5 StartOffset.4 StartOffset.3 StartOffset.2 StartOffset.1 StartOffset.0 Table 107 Description of EncodeStartOffset bits BIT 7 to 0 SYMBOL StartOffset<7:0> DESCRIPTION If enabled, WriteOn flags are delayed by EncodeStartOffset pulses of W441 when starting the encode process.
7.14.3
ENCODE STOP OFFSET REGISTER (ENCODESTOPOFFSET)
Table 108 Encode Stop Offset Register (address 32H) - WRITE 7 StopOffset.7 6 StopOffset.6 5 StopOffset.5 4 StopOffset.4 3 StopOffset.3 2 StopOffset.2 1 StopOffset.1 0 StopOffset.0
Table 109 Description of EncodeStopOffset bits BIT 7 to 0 SYMBOL StopOffset<7:0> DESCRIPTION If enabled, WriteOn flags are delayed by EncodeStopOffset pulses of W441 when stopping the encode process.
7.14.4
ENCODE XOFFSET REGISTER (ENCODEXOFFSET)
The 10-bit value for Xoffset must be written in two steps. EncodeXOffset can be written to in any order. XOffset<9:0> is a 2's complement number which gives a range of -511 to 511. Table 110 Encode XOffset Register (address 33H) - WRITE 7 0 0 6 0 1 5 XOffset.5 - 4 XOffset.4 - 3 XOffset.3 XOffset.9 2 XOffset.2 XOffset.8 1 XOffset.1 XOffset.7 0 XOffset.0 XOffset.6
Table 111 Description of EncodeXoffset bits BIT 7 to 0 SYMBOL XOffset<9:0> DESCRIPTION Offset applied to the phase error calculated between ATIPSync and Q-code sync.
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Channel encoder/decoder CDR60
7.15 The EFM modulator
SAA7392
This block takes data from the data encoder block and adds the subcode and synchronisation information. This data stream is modulated using EFM according to the Red Book standard. This data is output serially from the SAA7392, with the associated EFM clock signal. 7.15.1 EFM PRESET COUNT REGISTER (EFMPRESETCOUNT)
Table 112 EFM Preset Count Register (address 3CH) - WRITE 7 - 6 - 5 Count.5 4 Count.4 3 Count.3 2 Count.2 1 Count.1 0 Count.0
Table 113 Description of EFMPresetCount bits BIT 7 and 6 5 to 0 SYMBOL - Count<5:0> These 2 bits are reserved. This field can be used to program a position in an EFM frame for the modulator to start outputting data. DESCRIPTION
7.15.2
EFM MODULATOR CONFIGURATION REGISTER (EFMMODCONFIG)
Table 114 EFM Modulator Configuration Register (address 3DH) - WRITE 7 EFMClkSel 6 5 4 LWRTOn 3 GateClkOn 2 DataSel.1 1 DataSel.0 0 PanicOn
ModifiedEFM EnableLWRT
Table 115 Description of EFMModConfig bits BIT 7 6 5 4 3 2 1 0 SYMBOL EFMClkSel DESCRIPTION If EFMClkSel = 0, then EFM clock generator outputs normal XEFM frequency clock. If EFMClkSel = 1, then EFM clock generator outputs double frequency XEFM clock.
ModifiedEFM If ModifiedEFM = 0, then normal EFM output. If ModifiedEFM = 1, then all `0' output symbols are increased in length by one bit. EnableLWRT If EnableLWRT = 0, then LaserOn is off. If EnableLWRT = 1, then LaserOn will be set when WriteOn1 is turned on. LWRTOn GateClkOn DataSel.1 DataSel.0 PanicOn If LWRTOn = 0, then LaserOn determined by EnableLWRT bit. If LWRTOn = 1, then LaserOn output is enabled unconditionally. If GateClkOn = 0, then XEFM clock is on if WriteOn2 is set. If GateClkOn = 1, then XEFM clock is gated on unconditionally. These 2 bits along with the DataSel.2 bit in register EFMCON2 select the output data format; see Table 119. If PanicOn = 1, the Panic input is enabled. LaserOn will be disabled immediately when the PANIC pin (pin 27) is logic 1.
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Preliminary specification
Channel encoder/decoder CDR60
7.15.3 EFM MODULATOR CONFIGURATION REGISTER 2 (EFMMODCONFIG2))
SAA7392
Table 116 EFM Modulator Configuration Register 2 (address 3EH) - WRITE 7 - 6 - 5 - 4 - 3 - 2 TIM2Mode 1 TIM2ClkOn 0 DataSel.2
Table 117 Description of EFMModConfig2 bits BIT 7 to 3 2 1 0 SYMBOL - TIM2Mode TIM2ClkOn DataSel.2 This bit along with the DataSel.1 and DataSel.0 bits in register EFMModConfig select the output data format; see Table 119. These 5 bits are reserved. These 2 bits control the XEFM output; see Table 118. DESCRIPTION
Table 118 Control of the XEFM output TIM2Mode 0 1 1 TIM2ClkOn X 0 1 XEFM is operated according to GateClkOn bit setting in the EFMCON register (address 3DH). XEFM output is not influenced by LaserOn/WriteOn and is off. XEFM is gated on.
Table 119 Selection of output data format DataSel.2 0 0 0 0 1 X DataSel.1 0 0 1 1 0 X DataSel.0 0 1 0 1 1 X output normal data output I3 pattern output I11 pattern output special OPC pattern 3-3-4-4-5-5-6-6-7-7 All other settings are reserved. OUTPUT DATA FORMAT hold data output at zero
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Channel encoder/decoder CDR60
7.16 The EFM clock generator
SAA7392
The EFM clock generator will produce the recording clock based on one of three reference sources. There are five stages to the function. The first selects the reference source using a multiplexer. The next stage is a digital PLL to up-multiply the reference source. The source will determine the base frequency output by the PLL, whilst a position error signal is used to alter the frequency so that the position error tends to zero. Next, an analog PLL is used to up-multiply the output from the digital PLL. The output of the analog PLL is then multiplexed with an external source to allow the EFM clock generator to be bypassed completely. Finally, a programmable divider is used to enable the clock output, XEFM, to be doubled producing XEFM_2.
handbook, full pagewidth
W441 WCLK MUX DIGITAL PLL XError MUX Fifo filling Sysclk ANALOG PLL PROGRAMMABLE DIVIDER
Sysclk/192 MUX XEFM
Config Data
+
Kp
+
INTEGRATOR
MGR808
Ki
Fig.18 EFM PLL block diagram.
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Channel encoder/decoder CDR60
7.16.1 EFM CLOCK CONFIGURATION REGISTER 1 (EFMCLOCKCONF1)
SAA7392
Table 120 EFM Clock Configuration Register 1 (address 34H) - WRITE 7 DPLLBW.2 6 DPLLBW.1 5 DPLLBW.0 4 Bypass 3 Div.2 2 Div.1 1 Div.0 0 -
Table 121 Description of EFMClockConf1 bits BIT 7 6 5 4 3 2 1 0 SYMBOL DPLLBW.2 DPLLBW.1 DPLLBW.0 Bypass Div.2 Div.1 Div.0 - This bit is reserved. When Bypass = 0, then bypass is off. When Bypass = 1, then PLL is bypassed and the XEFM clock is derived from the system clock. These 3 bits select the analog PLL output divisor; see Table 123. DESCRIPTION These 3 bits select the digital PLL bandwidth; see Table 122.
Table 122 Selection of PLL bandwidth DPLLBW.2 0 0 0 0 1 DPLLBW.1 0 0 1 1 0 DPLLBW.0 0 1 0 1 0 PLL BANDWIDTH Digital PLL bandwidth is 400 Hz. Digital PLL bandwidth is 200 Hz. Digital PLL bandwidth is 100 Hz. Digital PLL bandwidth is 50 Hz. Digital PLL bandwidth is 25 Hz.
Table 123 Selection of analog PLL output divisor Div.2 0 0 0 0 1 1 1 1 Div.1 0 0 1 1 0 0 1 1 Div.0 0 1 0 1 0 1 0 1 PLL DIVISOR Analog PLL output is divided by 1 (XEFM_2 output is not available). Analog PLL output is divided by 2. Analog PLL output is divided by 3 (XEFM_2 output is not available). Analog PLL output is divided by 4. Analog PLL output is divided by 6. Analog PLL output is divided by 8. Analog PLL output is divided by 12. Analog PLL output is divided by 16.
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Channel encoder/decoder CDR60
7.16.2 EFM CLOCK CONFIGURATION REGISTER 2 (EFMCLOCKCONF2)
SAA7392
Table 124 EFM Clock Configuration Register 2 (address 35H) - WRITE 7 FreqSrc.1 6 FreqSrc.0 5 PosSrc.1 4 PosSrc.0 3 DPLLMF.3 2 DPLLMF.2 1 DPLLMF.1 0 DPLLMF.0
Table 125 Description of EFMClockConf2 bits BIT 7 6 5 4 3 2 1 0 SYMBOL FreqSrc.1 FreqSrc.0 PosSrc.1 PosSrc.0 DPLLMF.3 DPLLMF.2 DPLLMF.1 DPLLMF.0 These 4 bits select the multiplication factor for the PLL; see Table 128 These 2 bits select the position source; see Table 127. DESCRIPTION These 2 bits select the frequency source for the PLL; see Table 126.
Table 126 Selection of PLL frequency source FreqSrc.1 0 0 1 1 FreqSrc.0 0 1 0 1 FREQUENCY SOURCE PLL locks to W441. Use this signal as frequency source to lock EFM frequency to disc wobble. PLL locks to WCLK. Use this signal if encoding must slave to the word clock of some external I2S/EBU input. PLL locks to sysclock/192 This setting is reserved.
Table 127 Selection of position source PosSrc.1 0 1 1 X PosSrc.0 0 0 1 X No position error used. Position source is XError<6:0>. Use this source if EFM clock is locked to ATIP carrier (W441). Position source is FifoFill<6:0>. Use this source is EFM clock is locked to WCLK signal. All other combinations are reserved. POSITION SOURCE
Table 128 Digital PLL multiplication factor DPLLMF.3 0 0 0 0 0 1 1 2000 Mar 21 DPLLMF.2 0 0 0 1 1 0 0 DPLLMF.1 0 0 1 0 1 0 1 DPLLMF.0 0 1 0 0 0 0 0 294 196 147 98 73.5 49 36.75 56 DIGITAL PLL MULTIPLICATION FACTOR
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
7.16.3 EFM CLOCK CONFIGURATION REGISTER 3 (EFMCLOCKCONF3)
SAA7392
This is a dual-function register, the specific function is controlled by the state of bit 7. The integrator of the PI controller can be preset by writing to this register with the MSB set to logic 0. The value written is interpreted as a signed value. The current integrator value can be read back via this register. To program the Kp and Ki values, bit 7 of the EFMClockConf3 register must be logic 1. To determine the time constant of the I-branch, the sample frequency of the integrator must be known. This sample frequency is programmed via register EFMClockConf4 when the MSB is logic 1. The LSB is actually the switch to turn off the integrator path. The value in the integrator is not affected by programming this bit, so the integrator can be used as offset when Ki is logic 0. Table 129 EFM Clock Configuration Register 3 (address 36H) - READ/WRITE 7 0 1 6 IntegVal.6 Kp.2 5 IntegVal.5 Kp.1 4 IntegVal.4 Kp.0 3 IntegVal.3 Ki.3 2 IntegVal.2 Ki.2 1 IntegVal.1 Ki.1 0 IntegVal.0 Ki.0
Table 130 Selection of coefficient Kp Kp.2 0 0 0 0 1 Kp.1 0 0 1 1 0 Kp.0 0 1 0 1 0 4 2 1 0.5 0.25 COEFFICIENT Kp
Table 131 Selection of the coefficient Ki Ki.3 0 0 0 0 0 1 1 1 1 Ki.2 0 0 0 1 1 0 0 1 1 Ki.1 0 0 1 0 1 0 1 0 1 Ki.0 0 1 1 1 1 1 1 1 1 0 1 0.5 0.25 0.125 0.0625 0.03125 0.015625 0.0078125 COEFFICIENT Ki
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Channel encoder/decoder CDR60
7.16.4 EFM CLOCK CONFIGURATION REGISTER 4 (EFMCLOCKCONF4)
SAA7392
Good stability and critical damping of the integrator can be expected with a sample rate of 1/98 EFM frames and Ki = 2-7 at n = 2. The position error set-point may be programmed by writing to this register when the MSB is set to a logic 0. A position error setpoint between -64 and 63 can be programmed using the remaining 7 bits. On reset this register has the value -8.
This is a dual-function register, the specific function is controlled by the state of bit 7. The sample rate of the integrator may be programmed by writing to this register when the MSB is set to a logic 1. Higher sample rates let the integrator work faster. This is effectively the same as increasing the Ki value.
Table 132 EFM Clock Configuration Register 4 (address 37H) - WRITE 7 1 0 6 - PosErr.6 5 - PosErr.5 4 - PosErr.4 3 - PosErr.3 2 - PosErr.2 1 PosErr.1 0 PosErr.0
Samplerate.1 Samplerate.0
Table 133 Selection of the integrator sample rate Samplerate.1 Samplerate.0 0 0 1 1 0 1 0 1 392 196 98 49 SAMPLE RATE
Table 134 EFMPLL settings information INTENDED ENCODER SPEED n=1 n=2 n=4 DIGITAL MULTIPLICATION FACTOR 294 147 98 ANALOG PLL MULTIPLICATION FACTOR 4 4 4 PROGRAMMABLE DIVIDER FACTOR 12 6 4 POSITION ERROR TIME CONSTANT 2581 ms 635 ms 160 ms
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Preliminary specification
Channel encoder/decoder CDR60
7.17 The Wobble processor 7.17.3 THE ATIP BIT DETECTOR
SAA7392
The Wobble processor is a critical part of the recording process, and performs two main functions: * To extract the ATIP data from the wobble signal * To control the linear disc speed during recording. The Wobble processor comprises four functions, a front-end ADC, a digital PLL, the ATIP bit detector and the ATIP data read interface. 7.17.1 THE WOBBLE ADC FUNCTION
This function extracts the ATIP information bits from the ADC output and passes them to the ATIP read interface block. It also outputs the ATIPSync pulse. In order to protect the ATIPSyncs, a flywheel mechanism exists to interpolate ATIPSyncs if none are detected. This is a requirement to ensure that the recording process does not get corrupted. 7.17.4 THE ATIP READ INTERFACE
This converts the ATIP signal (WIN) to the digital domain. 7.17.2 THE WOBBLE PLL
The PLL has a PI type loop filter. The bandwidth of the loop and the integrator are programmable by the user. The user can also read and write the PLL frequency, the write mode is available to aid PLL lock-in. The block outputs a pulse signal at 44.1 kHz, which is phase modulated by the ATIP signal. 7.17.5
The ATIP data is read by the on-chip microprocessor. Data availability can be checked by polling the ATIPReady bit in the ATIP Status Register. The microprocessor must read both the ATIPData and ATIPDataEnd registers in order to complete the data read process correctly. If this does not happen, a status bit is set to warn the microcontroller.
WOBBLE CONFIGURATION REGISTER 1 (WOBBLECONFIG1)
This is a dual-function register, the specific function is determined by the state of bit 7. When bit 7 = 0, the function is as described in Tables 135 to 138. When bit 7 = 1, the function is as described in Tables 135 and 139. Table 135 Wobble Configuration Register 1 (address 27H) - WRITE 7 0 1 6 0 ATIPhold 5 PLLIntBW.2 - 4 PLLIntBW.1 WinWidth.4 3 PLLIntBW.0 WinWidth.3 2 LoopBW.2 1 LoopBW.1 0 LoopBW.0
WindWidth.2 WindWidth.1 WindWidth.0
Table 136 Description of WobbleConfig1 bits, bit 7 = 0 BIT 5 4 3 2 to 0 SYMBOL PLLIntBW.2 PLLIntBW.1 PLLIntBW.0 LoopBW<2:0> These 3 bits select the loop bandwidth; see Table 138. The PLL bandwidth is proportional to the system clock frequency and determines the following performance points: * Loop bandwidth should be approximately equal to bit rate to get good detector performance * Loop bandwidth depends on ATIP signal scaling. Current figures are valid for -6 dB scaling * PLL lock-in range is approximately equal to loop bandwidth. DESCRIPTION These 3 bits select the integrator bandwidth; see Table 137.
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Preliminary specification
Channel encoder/decoder CDR60
Table 137 Selection of integrator bandwidth PLLIntBW.2 0 0 0 0 1 1 1 1 PLLIntBW.1 0 0 1 1 0 0 1 1 PLLIntBW.0 0 1 0 1 0 1 0 1 INTEGRATOR BANDWIDTH 1.32 kHz for 4.26 MHz system clock 662 Hz for 4.26 MHz system clock 331 Hz for 4.26 MHz system clock 166 Hz for 4.26 MHz system clock 83 Hz for 4.26 MHz system clock 42 Hz for 4.26 MHz system clock 21 Hz for 4.26 MHz system clock 10 Hz for 4.26 MHz system clock
SAA7392
Table 138 Selection of loop bandwidth LOOPBW.2 0 0 0 0 1 1 1 1 LOOPBW.1 0 0 1 1 0 0 1 1 LOOPBW.0 0 1 0 1 0 1 0 1 LOOP BANDWIDTH 10.6 kHz for 4.26 MHz system clock 5.3 kHz for 4.26 MHz system clock 2.65 kHz for 4.26 MHz system clock 1.32 kHz for 4.26 MHz system clock 662 Hz for 4.26 MHz system clock 331 Hz for 4.26 MHz system clock 166 Hz for 4.26 MHz system clock 83 Hz for 4.26 MHz system clock
Table 139 Description of WobbleConfig1 bits, bit 7 = 1 BIT 6 5 4 3 2 1 0 SYMBOL ATIPhold - WinWidth.4 WinWidth.3 WinWidth.2 WinWidth.1 WinWidth.0 This bit is reserved. Determines the half of the width of the window where ATIP syncs are being accepted for resynchronization. The unit of WindowWidth is ATIP clock pulses. As an ATIP frame consists of 42 ATIP clock pulses, the maximum value of WindowWidth that can be programmed is 21. The reset value is logic 0. The OutOfWindow state can be detected by reading the ATIPStatus register. DESCRIPTION When ATIPhold = 1, then Wobble PLL in Hold mode.
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Preliminary specification
Channel encoder/decoder CDR60
7.17.6 WOBBLE CONFIGURATION REGISTER 2 (WOBBLECONFIG2)
SAA7392
Table 140 Wobble Configuration Register 2 (address 28H) - WRITE 7 - 6 - 5 PLLLBW.2 4 PLLLBW.1 3 PLLLBW.0 2 PLLHBW.2 1 PLLHBW.1 0 PLLHBW.0
Table 141 Description of WobbleConfig2 bits BIT 7 6 5 4 3 2 1 0 SYMBOL - - PLLLBW.2 PLLLBW.1 PLLLBW.0 PLLHBW.2 PLLHBW.1 PLLHBW.0 These 3 bits select the PLL high-pass bandwidth; see Table 142. These 3 bits select the PLL low-pass bandwidth; see Table 142. These 2 bits are reserved. DESCRIPTION
Table 142 Selection of the PLL high/low-pass bandwidth PLLLBW.2 PLLHBW.2 0 0 0 0 1 1 1 1 PLLLBW.1 PLLHBW.1 0 0 1 1 0 0 1 1 PLLLBW.0 HIGH/LOW-PASS BANDWIDTH PLLHBW.0 0 1 0 1 0 1 0 1 43 kHz for 4.26 MHz system clock 21.5 kHz for 4.26 MHz system clock 10.7 kHz for 4.26 MHz system clock 5.4 kHz for 4.26 MHz system clock 2.7 kHz for 4.26 MHz system clock 1.35 kHz for 4.26 MHz system clock 670 Hz for 4.26 MHz system clock 350 Hz for 4.26 MHz system clock
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Channel encoder/decoder CDR60
7.17.7 ATIP STATUS REGISTER (ATIPSTATUS)
SAA7392
Table 143 ATIP Status Register (address 29H) - READ 7 ATIPReady 6 Busy 5 CRCOK 4 - 3 - 2 - 1 SyncErr 0 OIS
Table 144 Description of ATIPStatus bits BIT 7 6 5 4 3 2 1 0 7.17.8 SYMBOL ATIPReady Busy CRCOK - - - SyncErr OIS If SyncErr = 1, then detected sync is not in-phase with the interpolated sync. Resync will be done on next detected sync. If OIS = 1, then sync has been interpolated, no detected sync. DESCRIPTION If ATIPReady = 0, then ATIP data is not ready. If ATIPReady = 1, then ATIP data is ready for read. Can also be an interrupt source. If Busy = 0, then ATIP data is not being read. If Busy = 1, then sub-CPU is busy reading ATIP data. If CRCOK = 0, then CRC check is not OK. If CRCOK = 1, then CRC check is OK. These 3 bits are reserved.
WOBBLE FREQUENCY REGISTER 1 (WOBBLEFREQ1)
Table 145 Wobble Frequency Register 1 (address 2AH) - WRITE/READ 7 PLLFreq.15 6 PLLFreq.14 5 PLLFreq.13 4 PLLFreq.12 3 PLLFreq.11 2 PLLFreq.10 1 PLLFreq.9 0 PLLFreq.8
Table 146 Description of WobbleFreq1 bits BIT 7 to 0 7.17.9 SYMBOL PLLFreq<15:8> DESCRIPTION These 8 bits form the most significant byte of the PLL frequency.
WOBBLE FREQUENCY REGISTER 2 (WOBBLEFREQ2)
Table 147 Wobble Frequency Register 2 (address 2BH) - READ/WRITE 7 PLLFreq.7 6 PLLFreq.6 5 PLLFreq.5 4 PLLFreq.4 3 PLLFreq.3 2 PLLFreq.2 1 PLLFreq.1 0 PLLFreq.0
Table 148 Description of WobbleFreq2 bits BIT 7 to 0 SYMBOL PLLFreq<7:0> DESCRIPTION These 8 bits form the least significant byte of the PLL frequency.
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Channel encoder/decoder CDR60
7.17.10 ATIP DATA REGISTER (ATIPDATA)
SAA7392
The upper 16 bits of the ATIP data can be obtained from this register by carrying out consecutive read operations. Table 149 ATIP Data Register (address 2CH) - READ 7 6 5 4 3 2 1 ATIPData.9 0 ATIPData.8
ATIPData.23 ATIPData.22 ATIPData.21 ATIPData.20 ATIPData.19 ATIPData.18 ATIPData.17 ATIPData.16 ATIPData.15 ATIPData.14 ATIPData.13 ATIPData.12 ATIPData.11 ATIPData.10 Table 150 Description of ATIPData bits BIT 7 to 0 7 to 0 SYMBOL ATIPData<23:16> ATIPData<15:8> DESCRIPTION most significant byte of ATIP data penultimate byte of ATIP data
7.17.11 ATIP DATA END REGISTER (ATIPDATAEND) Table 151 ATIP Data End Register (address 2DH) - READ 7 ATIPData.7 6 ATIPData.6 5 ATIPData.5 4 ATIPData.4 3 ATIPData.3 2 ATIPData.2 1 ATIPData.1 0 ATIPData.0
Table 152 Description of ATIPDataEnd bits BIT 7 to 0 SYMBOL ATIPData<7:0> DESCRIPTION least significant byte of ATIP data
7.17.12 WOBBLE PEAK STATUS REGISTER (WOBBLESTATUS) Table 153 Wobble Peak Status Register (address 2EH) - READ 7 WPPV.7 6 WPPV.6 5 WPPV.5 4 WPPV.4 3 WPPV.3 2 WPPV.2 1 WPPV.1 0 WPPV.0
Table 154 Description of WobbleStatus bits BIT 7 to 0 SYMBOL DESCRIPTION
WPPV<7:0> Peak value of the bit signal recovered by the Wobble processor.
7.17.13 ATIP ERROR REGISTER (ATER) This register is an unbuffered counter and is incremented on every ATIP code CRC error. When the register reaches 255 it will hold and is reset by being read. Table 155 ATIP Error Register (address 38H) - READ 7 ATER.7 6 ATER.6 5 ATER.5 4 ATER.4 3 ATER.3 2 ATER.2 1 ATER.1 0 ATER.0
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Channel encoder/decoder CDR60
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDDE VDDD VDDA Vi(max) VO VDDD IO IIK Tamb Tstg Ves1 Ves2 Notes PARAMETER supply voltage - pad output drivers supply voltage - core/pad ring supply voltage - analog maximum input voltage (any input) output voltage (any output) voltage difference between VDDA and VDDD output current (continuous) DC input diode current (continuous) operating ambient temperature storage temperature electrostatic handling electrostatic handling note 4 note 5 CONDITIONS notes 1 and 2 notes 1 and 2 notes 1 and 2 MIN. -0.5 -0.5 -0.5 -0.5 -0.5 - - - 0 -55 -1000 -100
SAA7392
MAX. +4.0 +4.0 +4.0 +5.0 note 3 0.25 20 20 +70 +125 +1000 +100 V V V V V V
UNIT
mA mA C C V V
1. All pad driver supply connections (VDDE) and analog and digital core/pad ring supply connections (VDDA and VDDD) must be made externally to the same power supply. 2. All VSS pins must be connected to the same external voltage. 3. (VDD + 0.5) or 4.1 V depending on which one is lower. 4. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor with a rise time of 15 ns. 5. Equivalent to discharging a 200 pF capacitor via a 0.75 H series inductor.
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Channel encoder/decoder CDR60
9 OPERATING CHARACTERISTICS PARAMETER CONDITIONS MIN. TYP.
SAA7392
SYMBOL Supply VDDD VDDA VDDE IDD
MAX.
UNIT
supply voltage (core/pad ring) supply voltage (analog) supply voltage (pad output drivers) supply current
3.0 3.0 3.0 -
3.3 3.3 3.3 200
3.6 3.6 3.6 -
V V V mA
Digital inputs SCL (CMOS) VIL VIH ILI Ci VIL VIH ILI Ci LOW-level input voltage HIGH-level input voltage input leakage current input capacitance Vi = 0 to VDD - 0.7VDD -10 - - 2.0 Vi = 0 to VDD -10 - - - - - - - - - 0.3VDD 5.0 +10 10 V V A pF
TEST1, TEST2, OTD, MUXSWI, PANIC, PORE, WRI, RDI, ALE, CSI, PCAIN, DATAI, SUB, SFSY, T2 AND T1 LOW-level input voltage HIGH-level input voltage input leakage current input capacitance 0.8 5.0 +10 10 V V A pF
Digital outputs W441, ATPSYC, CL1, INT, STOPCK, V4, EBUOUT, SYNC, FLAG, DATAO, RCK, LASERON, XEFM, EFMDATA, CFLG AND MEAS1 VOL VOH CL tr tf LOW-level output voltage HIGH-level output voltage load capacitance output rise time output fall time 0.4 to (VDD - 0.4); CL = 20 pF (VDD - 0.4) to 0.4; CL = 20 pF IOL = 4 mA IOH = -4 mA 0.4 to (VDD - 0.4); CL = 20 pF (VDD - 0.4) to 0.4; CL = 20 pF Vi = 0 to VDD IOL = 4 mA IOH = -4 mA - 0.85VDD - - - - - - - - 0.4 - 20 20 20 V V pF ns ns
MOTO1 (3-STATE) VOL VOH CL tr tf ILI Digital I/O DA7 TO DA0, WCLK, BCLK AND MOTO2/T3 VIL VIH 2000 Mar 21 LOW-level input voltage HIGH-level input voltage 65 - 0.7VDD - - 0.3VDD 5.0 V V LOW-level output voltage HIGH-level output voltage load capacitance output rise time output fall time 3-state leakage current - 0.85VDD - - - -10 - - - - - - 0.4 - 20 20 20 +10 V V pF ns ns A
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
SYMBOL ILI Ci VOL VOH CL tr tf
PARAMETER 3-state leakage current input capacitance LOW-level output voltage HIGH-level output voltage load capacitance output rise time output fall time
CONDITIONS Vi = 0 to VDD IOL = 4 mA IOH = -4 mA 0.4 to (VDD - 0.4); CL = 20 pF (VDD - 0.4) to 0.4; CL = 20 pF - -
MIN. -10 - - - - - - -
TYP.
MAX. +10 10 0.4 - 20 20 20
UNIT A pF V V pF ns ns
0.85VDD - - -
SDA (I2C-BUS) VIL VIH ILI Ci VOL IOL CL tf LOW-level input voltage HIGH-level input voltage 3-state leakage current input capacitance LOW-level output voltage LOW-level output current load capacitance output fall time CL = 20 pF IOL = 4 mA Vi = 0 to VDD - 0.7VDD -10 - 0 - - - - - - - - - - - 0.3VDD 5.0 +10 10 0.4 8 20 250 V V A pF V mA pF ns
Crystal oscillator XTLI (INPUT) VIL VIH ILI Ci fxtal gm Gv CF Co LOW-level input voltage HIGH-level input voltage input leakage current input capacitance - 0.7VDD -10 - 4 f = 100 kHz Gv = gm.RO - - - - - - - - 8 - - - - 0.3VDD 5.0 +10 - - - - - - V V A pF
XTLO (OUTPUT) crystal frequency mutual conductance small signal voltage gain feedback capacitance output capacitance MHz mA/V V/V pF pF
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Channel encoder/decoder CDR60
9.1 ADC and AGC parameters
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Table 156 ADC parameters PARAMETER Resolution Data format Maximum sample frequency SINAD DNL INL Power dissipation Input range Voltage reference Bias current Bandwidth Clock frequency Clock duty cycle Clock jitter 8-bit Simple Binary 70 MS/s >26 dB -1.0/+1.0 LSB -2.0/+2.0 LSB <100 mW 1.47 - 2.91 V 2.9 V 100 A 35 MHz 70 MHz 40 to 60% 200 ps for 6.5-bit accuracy, f = 17.5 MHz top ladder reference provided externally -3 dB (-0.5 effective bits) defines sample rate nominal rate 50 MS/s 17.5 MHz signal - 12 dB down on ADC full scale, 70 MS/s sample rate 70 MS/s; 1 MHz input 70 MS/s; 1 MHz input VALUE COMMENTS
Table 157 AGC parameters PARAMETER Output level Gain range Gain step Bandwidth Phase linearity Resolution SNR THD Input range Input impedance Offset voltage VALUE 1.4 V(p-p) -2.69 to +11.25 dB approx. linear in dBs 1.1 dB 35 MHz 0.6 ns 5-bit 50 dB <-35 dB 0.39 to 1.96 V 7.57 k <30 mV in bandwidth of 35 MHz f = 17.5 MHz; Vout(p-p) = 1.44 V; ADC load peak-to-peak value nominal, at HIN -3 dB point in bandwidth of 35 MHz COMMENTS
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Channel encoder/decoder CDR60
10 APPLICATION INFORMATION 10.1 Write start control of encoder in CD-ROM mode
SAA7392
2. Program the Wobble processor to capture ATIP time code from the disc. (Lock-in the wobble PLL). 3. Jump to a suitable time prior to the `record start address' (e.g. 10 frames). 4. Switch motor servo to ATIP signal. Allow enough time for motor speed to stabilize before start of write. Use motor monitor and wobble monitor functions for this. 5. Lock EFM PLL to I2S bit clock and FIFO filling. 6. Program encoder in `CD, encode, flush mode'. Program EFM modulator to WriteOn1 off and WriteOn2 on mode. Program input interface to digital silence. 7. Program the encoder to `CD, encode, normal mode'. The encoder will start streaming digital zero data. The operation of PLL locked to I2S bit clock and FIFO filling will regulate the FIFO filling toward a nominal value. 8. Program SubPresetCount and EFMPresetCount registers. 9. Initialize the subcode insert block. 10. Read ATIP time again. 11. Start encoding after suitable delay by writing to EncodeWriteControl. Turn on WriteOn1. 10.3 Start-up of encode in flow-control operation
In CD-ROM mode, the CDR60 is intended to operate in lock-to-disc mode during write. When writing is stopped by the Encode Control Block, the data flow through the device will also stop. All pointers will stop incrementing and the BCLK clock of the I2S input interface will stop. As a result, the buffer manager will stop outputting data to the CDR60. Write start will be given while the encoder is in this `hot stand-by' state, with all pointers stopped and all clocks stopped. It is extremely important to start the write from a precisely defined initial state. Hence, a `cold start' must be executed prior to the start of the write. This is as follows: 1. Start the CDR servo. Start the spindle motor servo in `tacho' mode. Start focus and radial servo loops. 2. Program the Wobble processor to capture ATIP time code data from the disc. (Lock-in the wobble PLL). 3. Jump to a suitable time prior to the `record start address'. (e.g. 10 frames.) 4. Switch motor servo to ATIP signal. Allow enough time for motor speed to stabilize before start of write. Use motor monitor and wobble monitor functions for this. 5. Lock EFM PLL to crystal clock. 6. Program encoder in `CD, encode, flush mode'. Program the EFM modulator to `WriteOn1, WriteOn2 off' mode. This is the reset state. 7. Reset the block encoder. 8. Program the encoder to `CD encode, normal mode'. The encoder will fill its internal tables, but data flow will stop after a while, because no EFM data is output. 9. Program SubPresetCount and EFMPresetCount registers. 10. Initialize the subcode insert block. 11. Read ATIP time again. 12. Start encoding after suitable delay by writing to EncodeWriteControl. Turn on both WriteOn1 and WriteOn2. 10.2 Write start control of encoder in Audio mode
1. Reset the encoder. Switch LaserOn off, switch WriteOn2 off and switch encoder to `flush' mode. 2. Preset the device. a) Preset the serial input format b) Preset the subcode insertion block c) Preset the EFM modulator block d) Preset the EFM clock generator. 3. Let the disc run at the correct speed, let the EFM clock generator produce the correct clock. 4. At this stage, the device is in Standby mode. Everything is initialized, the encoder is still in `reset' state and the I2S input clock is stopped. The encoder cannot accept data because it is reset. Because flow control is enabled the clock is stopped. 5. Initialize the block encoder pointers to point to the correct data from where encoding should start. 6. Switch the encoder from `flush' to `encode play' mode. At this point the encoder starts reading data from the serial interface but stops again after a few milliseconds because the its FIFO gets filled as the data out to the EFM modulator is still blocked.
In this mode the data flow is fixed speed as it is not possible to stop the data stream from the ADC to the CDR60. Because of this, a `hot start' is needed. 1. Start the CDR servo. Start the spindle motor servo in Tacho mode. Start focus and radial servo loops.
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Preliminary specification
Channel encoder/decoder CDR60
7. When the correct start address is found on the disc, the LaserOn and WriteOn2 signals are switched on at the same time. As a result data flow in the encoder starts while data is written to the disc. 10.4 Start-up of encoder in synchronous stream mode
SAA7392
7. When the correct start address is found on the disc LaserOn is switched on allowing data stream to the disc. 10.5 Operating CDR60 in CAV mode, flow control on input stream
In synchronous stream mode operation is different because the serial input stream cannot be gated off. 1. Reset the encoder. Switch LaserOn off, Switch WriteOn2 off and switch encoder to `flush' mode. 2. Preset the device. a) Preset the serial input format b) Preset the subcode insertion block c) Preset the EFM modulator block d) Preset the EFM clock generator. The EFM clock generator must be programmed to slave to the incoming serial stream. 3. Let the disc run at the required speed. Make the motor servo slave to the W441 wobble clock. 4. Switch on WriteOn2. This signal must be switched on to allow data to leave the encoder when it enters it. (Important to avoid overflow.) 5. At this stage everything is initialized. The input stream is running but does not enter the encoder because it is still in the `reset' state. The output stream is running too at the same speed as the input speed because the EFM clock generator is setup like this. 6. The encoder is switched from `flush' to `encode play' mode. At this point the data stream starts. Data from the serial in interface enters the encoder while data is read out from it at approximately the same speed via the EFM modulator. The FIFO will not overflow. The data is discarded and not written to the disc because LaserOn is still switch off.
For very high-speed operation it is possible to lock the EFM clock to the ATIP wobble carrier. To do this W441 must be selected as the clock source while the position error is taken from XError. The XError signal gives the time difference between the ATIPSync and the QSync. Programming the EFM clock generator like this with a multiplication factor of 98 will produce an EFM clock that is synchronous with the ATIP carrier. It can be used to write data in lock-to-disc mode. 10.6 Operating in CLV Mode, Flow Control on Input Stream
Simply bypass the EFM PLL and use the system clock as EFM source. 10.7 Operating in CLV Mode, Synchronous Stream Operation
When an audio stream is input to the CDR60 encoder the EFM clock must lock to the serial input WCLK clock signal. The position error is taken from the FIFOFill signal. This will produce an EFM clock that is 98 times the WCLK frequency.
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Preliminary specification
Channel encoder/decoder CDR60
11 PACKAGE OUTLINE LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SAA7392
SOT315-1
c
y X A 60 61 41 40 Z E
e E HE wM bp 80 1 pin 1 index 20 ZD bp D HD wM B vM B vM A L 21 detail X Lp A A2 A1 (A 3)
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.16 0.04 A2 1.5 1.3 A3 0.25 bp 0.27 0.13 c 0.18 0.12 D (1) 12.1 11.9 E (1) 12.1 11.9 e 0.5 HD HE L 1.0 Lp 0.75 0.30 v 0.2 w 0.15 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7 0o
o
14.15 14.15 13.85 13.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT315-1 REFERENCES IEC 136E15 JEDEC MS-026 EIAJ EUROPEAN PROJECTION
ISSUE DATE 99-12-27 00-01-19
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Channel encoder/decoder CDR60
12 SOLDERING 12.1 Introduction to soldering surface mount packages
SAA7392
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 12.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 12.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 12.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Channel encoder/decoder CDR60
12.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SAA7392
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
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Channel encoder/decoder CDR60
13 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7392
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 14 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 15 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Preliminary specification
Channel encoder/decoder CDR60
NOTES
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Preliminary specification
Channel encoder/decoder CDR60
NOTES
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Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/01/pp76
Date of release: 2000
Mar 21
Document order number:
9397 750 04685

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